From e4b65cc945bb5256fdb65041b9f4d20c05155cd8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 5 May 2023 20:46:11 +0200 Subject: soc/amd/common/data_fabric/domain: write _BBN method in SSDT Instead of having PCI0's _BBN method in the DSDT that always returns 0, use acpigen_write_BBN to generate the _BBN method that returns the first PCI bus number in the PCI domain/host bridge. TEST=On mandolin the _BBN method in the _SB/PCI0 scope is now in the SSDT instead of the DSDT, but still returns 0. Signed-off-by: Felix Held Change-Id: I8badeb0064b498d3f18217ea24bff73676913b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74992 Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/data_fabric/domain.c | 3 +++ src/soc/amd/picasso/acpi/northbridge.asl | 5 ----- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index aec1596fc1..c032fdb4bb 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -243,6 +243,9 @@ void amd_pci_domain_fill_ssdt(const struct device *domain) } acpigen_write_resourcetemplate_footer(); + + acpigen_write_BBN(domain->link_list->secondary); + /* Scope */ acpigen_pop_len(); } diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 688f138123..2f73ae4384 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -6,11 +6,6 @@ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ /* Describe the Northbridge devices */ -Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ -{ - Return(0) -} - Method(_STA, 0, NotSerialized) { Return(0x0f) /* Status is visible */ -- cgit v1.2.3