From e244986e40f0e3b9e08b2156bcc45f6fc18976d2 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 20 Oct 2014 18:04:29 -0700 Subject: rk3288: Increase PD_BUS_ACLK (SRAM clock) to improve boot speed This patch doubles the ACLK peripheral clock for the PD_BUS power domain to 297MHz, which is the closest to the maximum of 300MHz we can reach by dividing GPLL. This frequency directly translates into SRAM speed, so maximizing it has a huge impact on boot speed (especially with the lack of SRAM caching). BUG=chrome-os-partner:32987 TEST=Booted Veyron_Pinky. Hacked timestamps into vboot and confirmed that the (visibly) long signature verification times are nearly halved. Change-Id: Iafa3044854a4058a7f885c775119d964a6295de4 Signed-off-by: Patrick Georgi Original-Commit-Id: c230585f4344d0eab4f8eeaa761869965f2da08a Original-Change-Id: I3f19eaa3d97dcc6235d820c71eb5edf2ae87d647 Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/224524 Original-Trybot-Ready: Doug Anderson Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/9600 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/rockchip/rk3288/include/soc/clock.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index f17428da58..b8f892bbed 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -29,7 +29,8 @@ #define CPLL_HZ (384*MHz) #define NPLL_HZ (384*MHz) -#define PD_BUS_ACLK_HZ (148500*KHz) +/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */ +#define PD_BUS_ACLK_HZ (297000*KHz) #define PD_BUS_HCLK_HZ (148500*KHz) #define PD_BUS_PCLK_HZ (74250*KHz) -- cgit v1.2.3