From e13680bdd04f4d2128f024123784a9131f76faad Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 24 Jul 2013 03:57:49 -0700 Subject: exynos5420: Fix some clock settings Some registers and bit fields were wrong, but the difference is mostly academic since the code that uses them are never called. Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c Signed-off-by: Gabe Black Reviewed-on: https://gerrit.chromium.org/gerrit/63189 Reviewed-by: David Hendricks Reviewed-by: Hung-Te Lin Commit-Queue: Gabe Black Tested-by: Gabe Black Reviewed-on: http://review.coreboot.org/4385 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/samsung/exynos5420/clock.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 11e46d1b52..ed5b102d94 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -41,9 +41,9 @@ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { {12, 16, 24}, {-1, -1, -1}, {16, 0, 8}, /* PERIPH_ID_SROMC */ - {20, 16, 24}, - {24, 0, 8}, - {0, 0, 4}, + {20, 20, 24}, + {24, 24, 8}, + {28, 28, 4}, {4, 12, 16}, {-1, -1, -1}, {-1, -1, -1}, @@ -170,12 +170,9 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) break; case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: - src = readl(&clk->clk_src_peric1); - div = readl(&clk->clk_div_peric1); - break; case PERIPH_ID_SPI2: src = readl(&clk->clk_src_peric1); - div = readl(&clk->clk_div_peric2); + div = readl(&clk->clk_div_peric1); break; case PERIPH_ID_SPI3: case PERIPH_ID_SPI4: -- cgit v1.2.3