From e01e9b83f901aeb636b1d891c8cd3dbeee0dfcca Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Thu, 25 Aug 2022 14:22:47 +0200 Subject: mb/prodrive/atlas: Fix SMBUS/SPD addresses Commit 0e7cf3d81d121181a94b6a594b944628c2e5a939 (soc/intel/alderlake: Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5 SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the SoC code bug required commit 044883615d4471b7a0b883eb8b8224d95faf52af (mb/prodrive/atlas: Update correct SPD address) so that at least some RAM would work. Now that the SoC code bug is fixed, the workaround is no longer needed, so use the correct SPD address mapping. TEST=Boot Atlas and verify that both memory channels work Signed-off-by: Maximilian Brune Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/prodrive/atlas/romstage_fsp_params.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index 8aaef5bdfd..5afbab071a 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -35,9 +35,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, .smbus = { - [3] = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { .addr_dimm[0] = 0x52, - .addr_dimm[1] = 0x53, }, }, }; -- cgit v1.2.3