From dd52e17448b2a8b49c1add655aa3deb3adebbcbc Mon Sep 17 00:00:00 2001 From: Rudolf Marek Date: Sat, 15 Mar 2008 00:19:34 +0000 Subject: Following patch fixes the retrain/reset sequence which caused problem with some nVidia cards. The enable link should be enough, retrain is done there. Tested on my system. Signed-off-by: Rudolf Marek Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/via/k8t890/k8t890_pcie.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/src/southbridge/via/k8t890/k8t890_pcie.c b/src/southbridge/via/k8t890/k8t890_pcie.c index 7dcc5af09b..6a7acbbfed 100644 --- a/src/southbridge/via/k8t890/k8t890_pcie.c +++ b/src/southbridge/via/k8t890/k8t890_pcie.c @@ -41,8 +41,6 @@ static void peg_init(struct device *dev) * pci_write_config8(dev, 0xe2, 0x0); * pci_write_config8(dev, 0xe3, 0x92); */ - /* Disable scrambling bit 6 to 1. */ - pci_write_config8(dev, 0xc0, 0x43); /* Set replay timer limit. */ pci_write_config8(dev, 0xb1, 0xf0); @@ -62,18 +60,6 @@ static void peg_init(struct device *dev) reg = pci_read_config8(dev, 0x50); pci_write_config8(dev, 0x50, reg & ~0x10); - /* Retrain link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x20); - - reg = pci_read_config8(dev, 0x3e); - reg |= 0x40; /* Bus reset. */ - pci_write_config8(dev, 0x3e, reg); - - reg = pci_read_config8(dev, 0x3e); - reg &= ~0x40; /* Clear reset. */ - pci_write_config8(dev, 0x3e, reg); - dump_south(dev); } @@ -97,18 +83,6 @@ static void pcie_init(struct device *dev) reg = pci_read_config8(dev, 0x50); pci_write_config8(dev, 0x50, reg & ~0x10); - /* Retrain. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x20); - - reg = pci_read_config8(dev, 0x3e); - reg |= 0x40; /* Bus reset. */ - pci_write_config8(dev, 0x3e, reg); - - reg = pci_read_config8(dev, 0x3e); - reg &= ~0x40; /* Clear reset. */ - pci_write_config8(dev, 0x3e, reg); - dump_south(dev); } -- cgit v1.2.3