From dca74c16a377e8287bd3c4bbe0630a1a44343aab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 11 Dec 2018 15:16:29 +0100 Subject: Documentation/soc/intel/icelake: Fix references between documents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/c/30157 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick --- Documentation/mainboard/google/dragonegg.md | 4 ++-- Documentation/mainboard/intel/icelake_rvp.md | 4 ++-- Documentation/soc/intel/icelake/iceLake_coreboot_development.md | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/mainboard/google/dragonegg.md b/Documentation/mainboard/google/dragonegg.md index df4fe16d44..ef7e61b710 100644 --- a/Documentation/mainboard/google/dragonegg.md +++ b/Documentation/mainboard/google/dragonegg.md @@ -4,14 +4,14 @@ This page describes how to run coreboot on the google dragonegg board. Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` ## Building coreboot * Follow build instructions mentioned in Ice Lake document ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` * The default options for this board should result in a fully working image: diff --git a/Documentation/mainboard/intel/icelake_rvp.md b/Documentation/mainboard/intel/icelake_rvp.md index 09f2185b0b..514ba6b4dd 100644 --- a/Documentation/mainboard/intel/icelake_rvp.md +++ b/Documentation/mainboard/intel/icelake_rvp.md @@ -4,14 +4,14 @@ This page describes how to run coreboot on the Intel icelake_rvp board. Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` ## Building coreboot * Follow build instructions mentioned in Ice Lake document ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` * The default options for this board should result in a fully working image: diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md index 6f194cae15..5f8e279841 100644 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md @@ -17,12 +17,12 @@ Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel 2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC. ```eval_rst - :doc:`../../../mainboard/intel/icelake_rvp.md` + :doc:`../../../mainboard/intel/icelake_rvp` ``` 3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google ```eval_rst - :doc:`../../../mainboard/google/dragonegg.md` + :doc:`../../../mainboard/google/dragonegg` ``` ### Summary: -- cgit v1.2.3