From db735c478e12bebc8a2a4d3559f1ac8f1f15602f Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 25 Apr 2022 16:01:23 +0200
Subject: src: Remove unused <cf9_reset.h>

Found using:
diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<"

Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
---
 src/mainboard/intel/dcp847ske/early_southbridge.c | 1 -
 src/mainboard/roda/rk886ex/early_init.c           | 1 -
 src/northbridge/intel/ironlake/romstage.c         | 1 -
 src/security/intel/txt/romstage.c                 | 1 -
 src/soc/intel/broadwell/romstage.c                | 1 -
 src/soc/intel/common/block/acpi/acpi.c            | 1 -
 6 files changed, 6 deletions(-)

diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 92d49c1a2b..e2fd2aae9c 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -2,7 +2,6 @@
 
 #include <bootblock_common.h>
 #include <stdint.h>
-#include <cf9_reset.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c
index 76471ebe92..ddea82f46e 100644
--- a/src/mainboard/roda/rk886ex/early_init.c
+++ b/src/mainboard/roda/rk886ex/early_init.c
@@ -3,7 +3,6 @@
 #include <bootblock_common.h>
 #include <stdint.h>
 #include <arch/io.h>
-#include <cf9_reset.h>
 #include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index f7177826e5..1e6bf67e3e 100644
--- a/src/northbridge/intel/ironlake/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -3,7 +3,6 @@
 #include <arch/io.h>
 #include <stdint.h>
 #include <console/console.h>
-#include <cf9_reset.h>
 #include <device/pci_ops.h>
 #include <timestamp.h>
 #include <romstage_handoff.h>
diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c
index 98308b7ba1..e045c9d6fb 100644
--- a/src/security/intel/txt/romstage.c
+++ b/src/security/intel/txt/romstage.c
@@ -2,7 +2,6 @@
 
 #include <arch/cpu.h>
 #include <arch/mmio.h>
-#include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/cr.h>
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c
index 65fe7ec0c3..5c172ed2eb 100644
--- a/src/soc/intel/broadwell/romstage.c
+++ b/src/soc/intel/broadwell/romstage.c
@@ -2,7 +2,6 @@
 
 #include <acpi/acpi.h>
 #include <arch/romstage.h>
-#include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <elog.h>
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 78887e833b..2e6ee7c438 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -5,7 +5,6 @@
 #include <arch/cpu.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
-#include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/intel/msr.h>
-- 
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