From daecb1888ee813978a1d177a02ffd394445966a9 Mon Sep 17 00:00:00 2001 From: Scott Duplichan Date: Thu, 10 Feb 2011 20:49:56 +0000 Subject: According to AMD documentation, cache type WP should be used for execution from flash memory. Coreboot uses WB. While there is no noticeable performance difference between the two settings, use of WB can cause a problem for a jtag debugger. The attached patch changes AMD cache as ram setting for flash execution from WB to WP. Signed-off-by: Scott Duplichan Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/car/cache_as_ram.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7f66f363ef..26cdec3fbe 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -294,11 +294,11 @@ clear_fixed_var_mtrr_out: xorl %edx, %edx /* * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx -- cgit v1.2.3