From da60958ae37f15b6bc6f976bdf32b26fab573ae0 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Sat, 25 Jan 2020 13:42:53 +0100 Subject: superio/aspeed/ast2400: Fix Register Offset According to the specification the register offset must be 0x71 instead of 0x70. Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Felix Held --- src/superio/aspeed/ast2400/superio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 37a7c9d30c..6f2cbcdb70 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -35,7 +35,7 @@ static void ast2400_init(struct device *dev) pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); /* In ESPI mode must write 0 to IRQ level on every LDN */ - pnp_write_config(dev, 0x70, 0); + pnp_write_config(dev, 0x71, 0); pnp_exit_conf_mode(dev); } -- cgit v1.2.3