From d93a5bc1150726b637f398df2ea2d1da1f47627e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 15 Feb 2021 21:48:51 +0530 Subject: mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5 Assign 7-bit address of the targeted slave SPD. TEST=Able to read correct SPD data from SMBUS. Change-Id: If24e61b583638be7c055541c6eb126da28b542f6 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748 Tested-by: build bot (Jenkins) Reviewed-by: Meera Ravindranath Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/mainboard/intel/adlrvp/romstage_fsp_params.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 8a179d6d5b..c95d469a7c 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -39,12 +39,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) .topo = MEM_TOPO_DIMM_MODULE, .smbus = { [0] = { - .addr_dimm[0] = 0xa0, - .addr_dimm[1] = 0xa2, + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, }, [1] = { - .addr_dimm[0] = 0xa4, - .addr_dimm[1] = 0xa6, + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, }, }, }; -- cgit v1.2.3