From d8d43ba6ac5d1627262f9e60f44add01658ce692 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 27 Oct 2013 14:59:00 +0200 Subject: PCI ops: Rename pcie_xx() to pci_mmio_xx() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17530 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/include/arch/io.h | 54 ++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/pci_io_cfg.h | 10 ------ src/arch/x86/include/arch/pci_mmio_cfg.h | 32 ++++--------------- 3 files changed, 60 insertions(+), 36 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 0d1cadfb28..1ab69966a8 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -246,6 +246,60 @@ typedef u32 device_t; #include #include +static inline __attribute__((always_inline)) +uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config8(dev, where); + else + return pci_io_read_config8(dev, where); +} + +static inline __attribute__((always_inline)) +uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config16(dev, where); + else + return pci_io_read_config16(dev, where); +} + +static inline __attribute__((always_inline)) +uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config32(dev, where); + else + return pci_io_read_config32(dev, where); +} + +static inline __attribute__((always_inline)) +void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config8(dev, where, value); + else + pci_io_write_config8(dev, where, value); +} + +static inline __attribute__((always_inline)) +void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config16(dev, where, value); + else + pci_io_write_config16(dev, where, value); +} + +static inline __attribute__((always_inline)) +void pci_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config32(dev, where, value); + else + pci_io_write_config32(dev, where, value); +} + #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index b83853548e..434628586d 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -94,14 +94,4 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) outl(value, 0xCFC); } -#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_read_config8 pci_io_read_config8 -#define pci_read_config16 pci_io_read_config16 -#define pci_read_config32 pci_io_read_config32 - -#define pci_write_config8 pci_io_write_config8 -#define pci_write_config16 pci_io_write_config16 -#define pci_write_config32 pci_io_write_config32 -#endif - #endif /* _PCI_IO_CFG_H */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index d3eff8fab7..9b9f702630 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -18,11 +18,10 @@ #include -#if CONFIG_MMCONF_SUPPORT #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) +u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -30,7 +29,7 @@ u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) +u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -38,7 +37,7 @@ u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) +u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); @@ -46,7 +45,7 @@ u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) +void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -54,7 +53,7 @@ void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) +void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -62,30 +61,11 @@ void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) +void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); write32(addr, value); } -#define pci_mmio_read_config8 pcie_read_config8 -#define pci_mmio_read_config16 pcie_read_config16 -#define pci_mmio_read_config32 pcie_read_config32 - -#define pci_mmio_write_config8 pcie_write_config8 -#define pci_mmio_write_config16 pcie_write_config16 -#define pci_mmio_write_config32 pcie_write_config32 - -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_read_config8 pcie_read_config8 -#define pci_read_config16 pcie_read_config16 -#define pci_read_config32 pcie_read_config32 - -#define pci_write_config8 pcie_write_config8 -#define pci_write_config16 pcie_write_config16 -#define pci_write_config32 pcie_write_config32 -#endif - -#endif /* CONFIG_MMCONF_SUPPORT */ #endif /* _PCI_MMIO_CFG_H */ -- cgit v1.2.3