From d77525b5bd28011a56194fcb5f8f77bc709dd039 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 22 Aug 2022 17:07:58 -0500 Subject: vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h. Add/correct values for DDR5, LPDDR5, LPDDR5X. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Raul Rangel --- src/vendorcode/amd/fsp/mendocino/dmi_info.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/fsp/mendocino/dmi_info.h b/src/vendorcode/amd/fsp/mendocino/dmi_info.h index d2c26fad4c..bd9ac5f797 100644 --- a/src/vendorcode/amd/fsp/mendocino/dmi_info.h +++ b/src/vendorcode/amd/fsp/mendocino/dmi_info.h @@ -141,7 +141,9 @@ typedef enum { LpDdr2MemType, ///< Assign 28 to LPDDR2 LpDdr3MemType, ///< Assign 29 to LPDDR3 LpDdr4MemType, ///< Assign 30 to LPDDR4 - LpDdr5MemType, ///< Assign 31 to LPDDR5 + Ddr5MemType = 0x22, ///< Assign 34 to DDR5 + LpDdr5MemType, ///< Assign 35 to LPDDR5 + LpDdr5xMemType, ///< Assign 36 to LPDDR5X } DMI_T17_MEMORY_TYPE; /// DMI Type 17 offset 13h - Type Detail -- cgit v1.2.3