From d626e554aa6f2a15c2ac4c971d1e5d3a9405b5fc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 29 Oct 2020 21:56:40 +0100 Subject: soc/intel/broadwell/chip.h: Drop unused fields MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Broadwell boards now use the CPU code for Haswell. Therefore, these devicetree options are no longer used anywhere and can be removed. Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46995 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner --- src/soc/intel/broadwell/chip.h | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 9f6c58de47..045fdbc71c 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -31,34 +31,6 @@ struct soc_intel_broadwell_config { int cdclk; struct i915_gpu_controller_info gfx; - - /* - * Minimum voltage for C6/C7 state: - * 0x67 = 1.6V (full swing) - * ... - * 0x79 = 1.7V - * ... - * 0x83 = 1.8V (no swing) - */ - int vr_cpu_min_vid; - - /* - * Set slow VR ramp rate on C-state exit: - * 0 = Fast VR ramp rate / 2 - * 1 = Fast VR ramp rate / 4 - * 2 = Fast VR ramp rate / 8 - * 3 = Fast VR ramp rate / 16 - */ - int vr_slow_ramp_rate_set; - - /* Enable slow VR ramp rate */ - int vr_slow_ramp_rate_enable; - - /* Enable S0iX support */ - int s0ix_enable; - - /* TCC activation offset */ - uint32_t tcc_offset; }; typedef struct soc_intel_broadwell_config config_t; -- cgit v1.2.3