From d5a45470c816bc8a8bdc43951c9e4c4a592b55d3 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Thu, 15 Oct 2020 00:27:59 +0200 Subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 275e77df1a..637092be97 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -35,6 +35,8 @@ #include "chip.h" +#define CPUID_6_EAX_ISST (1 << 7) + /* * List of suported C-states in this processor. */ @@ -379,7 +381,7 @@ void generate_cpu_entries(const struct device *device) printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (config->speed_shift_enable) { + if (cpuid_eax(6) & CPUID_6_EAX_ISST) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); @@ -405,7 +407,7 @@ void generate_cpu_entries(const struct device *device) cores_per_package); } - if (config->speed_shift_enable) + if (cpuid_eax(6) & CPUID_6_EAX_ISST) acpigen_write_CPPC_method(); acpigen_pop_len(); -- cgit v1.2.3