From d540d740b6e76ece7a3fbd5d8803f652a176b50c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 23 Oct 2017 11:29:35 -0600 Subject: mainboard/google/kahlee: Prepare for variants Move files that are particularly specific to the mainboard into the variant directory. Files that only have small areas of mainboard specific pieces use #if to separate between the boards. Add memory.c to split out the variant board id into a weak function. Add baseboard/gpio.h to satisfy the build - this will be updated in the next commit. BUG=b:68293392 Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22185 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/kahlee/BiosCallOuts.c | 9 +- src/mainboard/google/kahlee/Kconfig | 12 +- src/mainboard/google/kahlee/Makefile.inc | 9 +- src/mainboard/google/kahlee/acpi/usb_oc.asl | 37 ------ src/mainboard/google/kahlee/boardid.c | 10 +- src/mainboard/google/kahlee/chromeos.c | 5 +- src/mainboard/google/kahlee/devicetree.cb | 64 --------- src/mainboard/google/kahlee/ec.h | 6 +- src/mainboard/google/kahlee/gpio.c | 145 -------------------- .../variants/baseboard/include/baseboard/gpio.h | 37 ++++++ .../baseboard/include/baseboard/variants.h | 24 ++++ .../google/kahlee/variants/kahlee/Makefile.inc | 22 ++++ .../google/kahlee/variants/kahlee/devicetree.cb | 64 +++++++++ src/mainboard/google/kahlee/variants/kahlee/gpio.c | 146 +++++++++++++++++++++ .../kahlee/variants/kahlee/include/acpi/usb_oc.asl | 37 ++++++ .../kahlee/variants/kahlee/include/variant/gpio.h | 39 ++++++ .../google/kahlee/variants/kahlee/memory.c | 29 ++++ 17 files changed, 424 insertions(+), 271 deletions(-) delete mode 100644 src/mainboard/google/kahlee/acpi/usb_oc.asl delete mode 100644 src/mainboard/google/kahlee/devicetree.cb delete mode 100644 src/mainboard/google/kahlee/gpio.c create mode 100644 src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h create mode 100644 src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h create mode 100644 src/mainboard/google/kahlee/variants/kahlee/Makefile.inc create mode 100644 src/mainboard/google/kahlee/variants/kahlee/devicetree.cb create mode 100644 src/mainboard/google/kahlee/variants/kahlee/gpio.c create mode 100644 src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl create mode 100644 src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h create mode 100644 src/mainboard/google/kahlee/variants/kahlee/memory.c diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index bf590ec137..f26b54e0ed 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -19,17 +19,18 @@ #include #include -extern const GPIO_CONTROL oem_kahlee_gpio[]; +extern const GPIO_CONTROL agesa_board_gpios[]; void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->EarlyOemGpioTable = (void *)oem_kahlee_gpio; + FchParams_reset->EarlyOemGpioTable = (void *)agesa_board_gpios; } void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { - FchParams_env->PostOemGpioTable = (void *)oem_kahlee_gpio; + FchParams_env->PostOemGpioTable = (void *)agesa_board_gpios; /* SDHCI/MMC configuration */ - FchParams_env->Sd.SdSlotType = 1; // EMMC + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)) + FchParams_env->Sd.SdSlotType = 1; // EMMC } diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 76e8eada8e..ddb1955c2b 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -35,9 +35,17 @@ config MAINBOARD_DIR string default google/kahlee +config VARIANT_DIR + string + default "kahlee" if BOARD_GOOGLE_KAHLEE + config MAINBOARD_PART_NUMBER string - default "Kahlee" + default "Kahlee" if BOARD_GOOGLE_KAHLEE + +config DEVICETREE + string + default "variants/${CONFIG_VARIANT_DIR}/devicetree.cb" config MAX_CPUS int @@ -66,7 +74,7 @@ config CHROMEOS config GBB_HWID string depends on CHROMEOS - default "KAHLEE TEST 6421" + default "KAHLEE TEST 6421" if BOARD_GOOGLE_KAHLEE config AMD_FWM_POSITION_INDEX int diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index fb381bf554..131eba38c5 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -17,22 +17,25 @@ bootblock-y += bootblock/bootblock.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock/OemCustomize.c bootblock-y += ec.c -bootblock-y += gpio.c romstage-y += BiosCallOuts.c romstage-y += boardid.c romstage-y += chromeos.c -romstage-y += gpio.c romstage-y += OemCustomize.c ramstage-y += BiosCallOuts.c ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += ec.c -ramstage-y += gpio.c ramstage-y += OemCustomize.c verstage-y += chromeos.c verstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/kahlee/acpi/usb_oc.asl b/src/mainboard/google/kahlee/acpi/usb_oc.asl deleted file mode 100644 index 068d6fd96d..0000000000 --- a/src/mainboard/google/kahlee/acpi/usb_oc.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* - * DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - * { - * #include "usb.asl" - * } - */ - -/* USB overcurrent mapping pins. */ -Name (UOM0, 0) -Name (UOM1, 2) -Name (UOM2, 0) -Name (UOM3, 7) -Name (UOM4, 2) -Name (UOM5, 2) -Name (UOM6, 6) -Name (UOM7, 2) -Name (UOM8, 6) -Name (UOM9, 6) - -/* USB Overcurrent GPEs */ diff --git a/src/mainboard/google/kahlee/boardid.c b/src/mainboard/google/kahlee/boardid.c index f19b032526..5b59f329bd 100644 --- a/src/mainboard/google/kahlee/boardid.c +++ b/src/mainboard/google/kahlee/boardid.c @@ -16,19 +16,15 @@ #include #include #include +#include +#include uint8_t board_id(void) { MAYBE_STATIC int id = -1; - gpio_t gpios[] = { - GPIO_135, - GPIO_140, - GPIO_144, - }; - if (id < 0) { - id = gpio_base2_value(gpios, ARRAY_SIZE(gpios)); + id = variant_board_id(); printk(BIOS_SPEW, "Board ID: %#x.\n", id); } diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 55130741d7..e74e3b9970 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -19,10 +19,7 @@ #include #include #include - -/* SPI Write protect */ -#define CROS_WP_GPIO GPIO_142 -#define GPIO_EC_IN_RW GPIO_15 +#include void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/google/kahlee/devicetree.cb b/src/mainboard/google/kahlee/devicetree.cb deleted file mode 100644 index 4376011797..0000000000 --- a/src/mainboard/google/kahlee/devicetree.cb +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip soc/amd/stoneyridge - - register "spdAddrLookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - - device cpu_cluster 0 on - device lapic 10 on end - end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # M.2 slot - device pci 2.3 on end # M.2 slot - device pci 2.4 on end # x1 PCIe slot - device pci 2.5 on end # Cardreader - # devices on the NB/SB Link, but on the same pci bus - device pci 8.0 on end # PSP - device pci 9.0 on end # PCIe Host Bridge - device pci 9.2 on end # HDA - device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI - device pci 14.0 on # SM - chip drivers/generic/generic # dimm 0-0-0 - device i2c 50 on end - end - end # SM - device pci 14.3 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC 0x790e - device pci 14.7 on end # SD - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - end #domain -end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/ec.h b/src/mainboard/google/kahlee/ec.h index 495ad692e4..3986aed63c 100644 --- a/src/mainboard/google/kahlee/ec.h +++ b/src/mainboard/google/kahlee/ec.h @@ -18,11 +18,7 @@ #include #include - -/* AGPIO22 -> GPE3 */ -#define EC_SCI_GPI 3 -/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */ -#define EC_SMI_GPI 23 +#include #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/gpio.c deleted file mode 100644 index 7072b13248..0000000000 --- a/src/mainboard/google/kahlee/gpio.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -const GPIO_CONTROL oem_kahlee_gpio[] = { - /* AGPIO2 PCIE/WLAN WAKE# SCI*/ - {2, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* SER TX */ - {8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - /* SER RX */ - {9, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* AGPIO 12 */ - {12, Function2, FCH_GPIO_PULL_UP_ENABLE }, - - /* TS_EN_SOC (TouchScreen enable GPIO) */ - {13, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - - /* CAM_PWRON (Camera enable GPIO) */ - {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - - /* EC_IN_RW */ - {15, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* APU_I2C_3_SCL */ - {19, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* APU_I2C_3_SDA */ - {20, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* AGPIO22 EC_SCI */ - {22, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* APU_BT_ON# */ - {24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - - /* DEVSLP1_SSD */ - {67, Function1, FCH_GPIO_PULL_UP_ENABLE}, - - /* DEVSLP1_EMMC */ - /* No Connect for now. - * {70, Function1, FCH_GPIO_PULL_UP_ENABLE}, - */ - - /* SPI_TPM_CS_L */ - {76, Function1, FCH_GPIO_PULL_DOWN_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - - /* CAM_LED# */ - {84, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - - /* TS_RST# (TouchScreen Reset) */ - {85, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - - /* WLAN_RST#_AUX */ - {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, - - /* BD_ID1 */ - {135, Function1, 0 }, - - /* TPM_SERIRQ# */ - {139, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* BD_ID2 */ - {140, Function1, 0 }, - - /* APU_SPI_WP */ - {142, Function1, FCH_GPIO_PULL_UP_ENABLE }, - - /* BD_ID3 */ - {144, Function1, 0 }, - - {-1} -}; - -/* - * GPE setup table must match ACPI GPE ASL - * { gevent, gpe, direction, level } - */ -static const struct sci_source gpe_table[] = { - - /* EC AGPIO22/Gevent3 -> GPE 3 */ - { - .scimap = 3, - .gpe = 3, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_EDG, - }, - - /* PCIE/WLAN AGPIO2/Gevent8 -> GPE8 */ - { - .scimap = 8, - .gpe = 8, - .direction = SMI_SCI_LVL_LOW, - .level = SMI_SCI_LVL, - }, - - /* EHCI USB_PME -> GPE24 */ - { - .scimap = 24, - .gpe = 24, - .direction = SMI_SCI_LVL_HIGH, - .level = SMI_SCI_LVL, - }, - - /* XHCIC0 -> GPE31 */ - { - .scimap = 56, - .gpe = 31, - .direction = SMI_SCI_LVL_HIGH, - .level = SMI_SCI_LVL, - }, -}; - -const struct sci_source *get_gpe_table(size_t *num) -{ - *num = ARRAY_SIZE(gpe_table); - return gpe_table; -} diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..5aca3e88b5 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#ifndef __ACPI__ +#include + +# define MEM_CONFIG0 GPIO_0 +# define MEM_CONFIG1 GPIO_0 +# define MEM_CONFIG2 GPIO_0 +# define MEM_CONFIG3 GPIO_0 + +/* SPI Write protect */ +#define CROS_WP_GPIO GPIO_0 +#define GPIO_EC_IN_RW GPIO_0 + +#endif /* _ACPI__ */ + +#define EC_SCI_GPI 0 + +#define EC_SMI_GPI 0 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..3b4da2636b --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include + +size_t variant_board_id(void); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc new file mode 100644 index 0000000000..94f388912c --- /dev/null +++ b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += memory.c diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb new file mode 100644 index 0000000000..4376011797 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb @@ -0,0 +1,64 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + + register "spdAddrLookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # M.2 slot + device pci 2.3 on end # M.2 slot + device pci 2.4 on end # x1 PCIe slot + device pci 2.5 on end # Cardreader + # devices on the NB/SB Link, but on the same pci bus + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + end + end # SM + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC 0x790e + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c new file mode 100644 index 0000000000..e25f1a1e42 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +const GPIO_CONTROL agesa_board_gpios[] = { + /* AGPIO2 PCIE/WLAN WAKE# SCI*/ + {2, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* SER TX */ + {8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + /* SER RX */ + {9, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* AGPIO 12 */ + {12, Function2, FCH_GPIO_PULL_UP_ENABLE }, + + /* TS_EN_SOC (TouchScreen enable GPIO) */ + {13, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + + /* CAM_PWRON (Camera enable GPIO) */ + {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + + /* EC_IN_RW */ + {15, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* APU_I2C_3_SCL */ + {19, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* APU_I2C_3_SDA */ + {20, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* AGPIO22 EC_SCI */ + {22, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* APU_BT_ON# */ + {24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + + /* DEVSLP1_SSD */ + {67, Function1, FCH_GPIO_PULL_UP_ENABLE}, + + /* DEVSLP1_EMMC */ + /* No Connect for now. + * {70, Function1, FCH_GPIO_PULL_UP_ENABLE}, + */ + + /* SPI_TPM_CS_L */ + {76, Function1, FCH_GPIO_PULL_DOWN_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + + /* CAM_LED# */ + {84, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + + /* TS_RST# (TouchScreen Reset) */ + {85, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + + /* WLAN_RST#_AUX */ + {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + + /* BD_ID1 */ + {135, Function1, 0 }, + + /* TPM_SERIRQ# */ + {139, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* BD_ID2 */ + {140, Function1, 0 }, + + /* APU_SPI_WP */ + {142, Function1, FCH_GPIO_PULL_UP_ENABLE }, + + /* BD_ID3 */ + {144, Function1, 0 }, + + {-1} +}; + +/* + * GPE setup table must match ACPI GPE ASL + * { gevent, gpe, direction, level } + */ +static const struct sci_source gpe_table[] = { + + /* EC AGPIO22/Gevent3 -> GPE 3 */ + { + .scimap = 3, + .gpe = 3, + .direction = SMI_SCI_LVL_LOW, + .level = SMI_SCI_EDG, + }, + + /* PCIE/WLAN AGPIO2/Gevent8 -> GPE8 */ + { + .scimap = 8, + .gpe = 8, + .direction = SMI_SCI_LVL_LOW, + .level = SMI_SCI_LVL, + }, + + /* EHCI USB_PME -> GPE24 */ + { + .scimap = 24, + .gpe = 24, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_LVL, + }, + + /* XHCIC0 -> GPE31 */ + { + .scimap = 56, + .gpe = 31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_LVL, + }, +}; + +const struct sci_source *get_gpe_table(size_t *num) +{ + *num = ARRAY_SIZE(gpe_table); + return gpe_table; +} diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl new file mode 100644 index 0000000000..068d6fd96d --- /dev/null +++ b/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* + * DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + * { + * #include "usb.asl" + * } + */ + +/* USB overcurrent mapping pins. */ +Name (UOM0, 0) +Name (UOM1, 2) +Name (UOM2, 0) +Name (UOM3, 7) +Name (UOM4, 2) +Name (UOM5, 2) +Name (UOM6, 6) +Name (UOM7, 2) +Name (UOM8, 6) +Name (UOM9, 6) + +/* USB Overcurrent GPEs */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h new file mode 100644 index 0000000000..dfb6354a3e --- /dev/null +++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __VARIANT_GPIO_H__ +#define __VARIANT_GPIO_H__ + +#ifndef __ACPI__ +#include + +#define MEM_CONFIG0 GPIO_135 +#define MEM_CONFIG1 GPIO_140 +#define MEM_CONFIG2 GPIO_144 + +/* SPI Write protect */ +#define CROS_WP_GPIO GPIO_142 +#define GPIO_EC_IN_RW GPIO_15 + +#endif /* _ACPI__ */ + +/* AGPIO22 -> GPE3 */ +#define EC_SCI_GPI 3 + +/* TODO: Fix this */ +/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 23 + +#endif /* __VARIANT_GPIO_H__ */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/memory.c b/src/mainboard/google/kahlee/variants/kahlee/memory.c new file mode 100644 index 0000000000..4341b824b5 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/kahlee/memory.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include /* src/include/gpio.h */ +#include +#include + +size_t variant_board_id(void) +{ + gpio_t pads[] = { + [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, + [0] = MEM_CONFIG0, + }; + + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +} -- cgit v1.2.3