From d453081a57508e25f6d46223e1e8a0f6f93c85ce Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 12 Oct 2018 10:46:17 -0600 Subject: soc/amd/stoneyridge: Define PM USB Enable register Make #define definitions for PMxEF and replace the hardcoded values. Note that this doesn't change the current functionality of the source. The existing code has been propogated from the sb//hudson port, which seems to attempt to enable 100% of all OHCI and EHCI controllers that may be present in the system. Change-Id: I6018b0062730de19e3283a010144dfedc2b11423 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/29075 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/enable_usbdebug.c | 4 ++-- src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 0a0c3ec66d..27ac61f980 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -26,8 +26,8 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { /* Enable all of the USB controllers */ - outb(0xef, PM_INDEX); - outb(0x7f, PM_DATA); + outb(PM_USB_ENABLE, PM_INDEX); + outb(PM_USB_ALL_CONTROLLERS, PM_DATA); return SOC_EHCI1_DEV; } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ce0af95a20..b9dc62a76e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -101,6 +101,8 @@ #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM_USB_ENABLE 0xef +#define PM_USB_ALL_CONTROLLERS 0x7f /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 -- cgit v1.2.3