From d42125cb95c75270dbccce1e038a9aa7e5aaca4f Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Sat, 27 Jan 2024 04:19:41 +0800
Subject: MAINTAINERS: Add Sapphire Rapids FSP header path to Xeon SP

Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8b4f26d515..d09307133a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -948,6 +948,7 @@ S:	Supported
 F:	src/soc/intel/xeon_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/skylake_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/
+F:	src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/
 
 MEDIATEK SOCS
 M:	Hung-Te Lin <hungte@chromium.org>
-- 
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