From d39c68a0c034f478cf933bf101d7a62253cc8d02 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 5 Jun 2017 13:26:14 -0700 Subject: soc/intel/cannonlake: Add UART initialization Cannonlake has built-in UART driver as part of LPSS block. However port mapped decoders are in use as well. Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/20063 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/uart.c | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 src/soc/intel/cannonlake/uart.c diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c new file mode 100644 index 0000000000..6f5fb6d7e9 --- /dev/null +++ b/src/soc/intel/cannonlake/uart.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Clock divider parameters for 115200 baud rate */ +#define CLK_M_VAL 0x30 +#define CLK_N_VAL 0xc35 + +static const struct port { + struct pad_config pads[2]; /* just TX and RX */ + device_t dev; +} uart_ports[] = { + {.dev = PCH_DEV_UART0, + .pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1)} /* TX */ + }, + {.dev = PCH_DEV_UART1, + .pads = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1)} /* TX */ + }, + {.dev = PCH_DEV_UART2, + .pads = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */ + } +}; + +void pch_uart_init(void) +{ + uintptr_t base; + const struct port *p; + + assert(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(uart_ports)); + p = &uart_ports[CONFIG_UART_FOR_CONSOLE]; + base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + + uart_common_init(p->dev, base, CLK_M_VAL, CLK_N_VAL); + gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads)); +} + +uintptr_t uart_platform_base(int idx) +{ + /* We can only have one serial console at a time */ + return UART_DEBUG_BASE_ADDRESS; +} -- cgit v1.2.3