From d211ede937c9352b3a90d98871d128d858e3f21b Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Tue, 16 Mar 2021 11:39:30 -0600
Subject: mb/amd/majolica: Generate OIPG Package

This fixes the unknown reference errors for OIPG. Since Majolica
doesn't actually have any of the GPIOs ChromeOS uses, we leave
the arrays empty.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/majolica/Makefile.inc |  2 ++
 src/mainboard/amd/majolica/chromeos.c   | 26 ++++++++++++++++++++++++++
 src/mainboard/amd/majolica/mainboard.c  |  3 +++
 3 files changed, 31 insertions(+)
 create mode 100644 src/mainboard/amd/majolica/chromeos.c

diff --git a/src/mainboard/amd/majolica/Makefile.inc b/src/mainboard/amd/majolica/Makefile.inc
index 3a9f367eee..64f86bde34 100644
--- a/src/mainboard/amd/majolica/Makefile.inc
+++ b/src/mainboard/amd/majolica/Makefile.inc
@@ -3,6 +3,8 @@
 bootblock-y += bootblock.c
 bootblock-y += early_gpio.c
 
+ramstage-y += chromeos.c
+
 APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
 APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin
 
diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c
new file mode 100644
index 0000000000..c73e047933
--- /dev/null
+++ b/src/mainboard/amd/majolica/chromeos.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	/* Majolica doesn't have a write protect pin */
+	return 0;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	/* No ChromeOS GPIOs */
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c
index b38184076e..1a7be4be29 100644
--- a/src/mainboard/amd/majolica/mainboard.c
+++ b/src/mainboard/amd/majolica/mainboard.c
@@ -7,6 +7,7 @@
 #include <soc/acpi.h>
 #include <string.h>
 #include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /*
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -94,6 +95,8 @@ static void mainboard_enable(struct device *dev)
 	init_tables();
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();
+
+	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
-- 
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