From d13118320030c6df48ad33243d48c3ff34cb67d7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 11 Aug 2019 17:48:44 +0200 Subject: nb/intel/gm45: Split DDR2 I/O init out Move DDR3 memory I/O init to its own function and add DDR2 memory I/O init. Read I/O init is common to both DDR2 and DDR3. TEST: DDR2 systems boot (with the rest of the patch train) - Tested on a Dell Latitude E6400 - Tested on a Compal JHL90 TEST: Ensure DDR3 systems still boot - Tested on a Thinkpad X200 Change-Id: Ic4d5130f527249d3a5b98bae778cdf21a1753b04 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34833 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/raminit.c | 136 ++++++++++++++++++++++++++++++++--- 1 file changed, 125 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a57f201d4f..8a72d4afba 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1498,6 +1498,7 @@ static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, ((( clk1067 && !cardF[ch])?3:2) << 11) | mixed); } } + static void ddr3_write_io_init(const mem_clock_t ddr3clock, const dimminfo_t *const dimms, const stepping_t stepping, @@ -1564,9 +1565,10 @@ static void ddr3_write_io_init(const mem_clock_t ddr3clock, mchbar_write32(0x1590, 0x00e70067); mchbar_write32(0x1594, 0x000d8000); } -static void ddr3_read_io_init(const mem_clock_t ddr3clock, - const dimminfo_t *const dimms, - const int sff) + +static void ddr_read_io_init(const mem_clock_t ddr_clock, + const dimminfo_t *const dimms, + const int sff) { int ch; @@ -1577,7 +1579,7 @@ static void ddr3_read_io_init(const mem_clock_t ddr3clock, tmp = mchbar_read32(addr); tmp &= ~((3 << 25) | (1 << 8) | (7 << 16) | (0xf << 20) | (1 << 27)); tmp |= (1 << 27); - switch (ddr3clock) { + switch (ddr_clock) { case MEM_CLOCK_667MT: tmp |= (1 << 16) | (4 << 20); break; @@ -1598,10 +1600,10 @@ static void ddr3_read_io_init(const mem_clock_t ddr3clock, } } -static void memory_io_init(const mem_clock_t ddr3clock, - const dimminfo_t *const dimms, - const stepping_t stepping, - const int sff) +static void ddr3_memory_io_init(const mem_clock_t ddr3clock, + const dimminfo_t *const dimms, + const stepping_t stepping, + const int sff) { u32 tmp; @@ -1694,7 +1696,114 @@ static void memory_io_init(const mem_clock_t ddr3clock, ddr3_write_io_init(ddr3clock, dimms, stepping, sff); - ddr3_read_io_init(ddr3clock, dimms, sff); + ddr_read_io_init(ddr3clock, dimms, sff); +} + +static void ddr2_select_clock_mux(const dimminfo_t *const dimms) +{ + int ch; + unsigned int o; + FOR_EACH_POPULATED_CHANNEL(dimms, ch) { + const unsigned int b = 0x14b0 + (ch * 0x0100); + for (o = 0; o < 0x20; o += 4) + mchbar_clrbits32(b + o, 7 << 11); + } +} + +static void ddr2_write_io_init(const dimminfo_t *const dimms) +{ + int s; + + mchbar_clrsetbits32(CxWRTy_MCHBAR(0, 0), 0xf7bff71f, 0x008b0008); + + for (s = 1; s < 4; ++s) { + mchbar_clrsetbits32(CxWRTy_MCHBAR(0, s), 0xf7bff71f, 0x00800000); + } + + mchbar_clrsetbits32(0x1490, 0xf7fff77f, 0x00800000); + mchbar_clrsetbits32(0x1494, 0xf71f8000, 0x00040000); + + mchbar_clrsetbits32(CxWRTy_MCHBAR(1, 0), 0xf7bff71f, 0x00890008); + + for (s = 1; s < 4; ++s) { + mchbar_clrsetbits32(CxWRTy_MCHBAR(1, s), 0xf7bff71f, 0x00890000); + } + + mchbar_clrsetbits32(0x1590, 0xf7fff77f, 0x00800000); + mchbar_clrsetbits32(0x1594, 0xf71f8000, 0x00040000); +} + +static void ddr2_memory_io_init(const mem_clock_t ddr2clock, + const dimminfo_t *const dimms, + const stepping_t stepping, + const int sff) +{ + u32 tmp; + u32 tmp2; + + if (stepping < STEPPING_B1) + die("Stepping fsb_clock); /* Perform system-memory i/o initialization. */ - memory_io_init(timings->mem_clock, dimms, - sysinfo->stepping, sysinfo->sff); + if (sysinfo->spd_type == DDR2) { + ddr2_memory_io_init(timings->mem_clock, dimms, + sysinfo->stepping, sysinfo->sff); + } else { + ddr3_memory_io_init(timings->mem_clock, dimms, + sysinfo->stepping, sysinfo->sff); + } /* Initialize memory map with dummy values of 128MB per rank with a page size of 4KB. This makes the JEDEC initialization code easier. */ -- cgit v1.2.3