From d0627c7595feb580c8c03f0335644b85bbc842aa Mon Sep 17 00:00:00 2001 From: Jan Samek Date: Fri, 9 Jun 2023 13:11:45 +0200 Subject: mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1 It's been decided not to use the USB 3.0 port 1 on this board anymore, so disable it also with the corresponding USB 2.0 lane. BUG=none TEST=USB 3.0 port 1 not functional anymore after boot, while others continue working. Change-Id: I2799e3d9d7232743c9480dd9611d94ed3249f53b Signed-off-by: Jan Samek Reviewed-on: https://review.coreboot.org/c/coreboot/+/75702 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Eric Lai --- src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb index 9810a90614..16f4375e63 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/elkhartlake # USB related UPDs register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X125/X135 - register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # X125/X135 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # UNUSED register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # X145/X155 register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # X145/X155 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB Panel @@ -32,7 +32,7 @@ chip soc/intel/elkhartlake register "usb2_ports[9]" = "USB2_PORT_EMPTY" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # UNUSED register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED -- cgit v1.2.3