From d047927168e63004d0b4fa521b48d321af1b0ac6 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Fri, 28 May 2021 20:00:02 +0530 Subject: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines The patch configures 4KB memory region window for each of the TBT DMA remapping engine. So, the remap engines map their register set to the respective 4KB window. TEST=Verified boot on Brya Signed-off-by: Sridhar Siricilla Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55015 Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/romstage/fsp_params.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index ba6e036a2e..fdfb65b6d9 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -32,6 +32,10 @@ enum vtd_base_index_type { VTD_GFX, VTD_IPU, VTD_VTVCO, + VTD_TBT0, + VTD_TBT1, + VTD_TBT2, + VTD_TBT3, }; static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) @@ -228,6 +232,21 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, printk(BIOS_ERR, "ERROR: Requested VT-d, but VTVCO_BASE_ADDRESS is 0\n"); } + if (m_cfg->TcssDma0En || m_cfg->TcssDma1En) + m_cfg->VtdItbtEnable = 1; + + if (m_cfg->TcssItbtPcie0En) + m_cfg->VtdBaseAddress[VTD_TBT0] = TBT0_BASE_ADDRESS; + + if (m_cfg->TcssItbtPcie1En) + m_cfg->VtdBaseAddress[VTD_TBT1] = TBT1_BASE_ADDRESS; + + if (m_cfg->TcssItbtPcie2En) + m_cfg->VtdBaseAddress[VTD_TBT2] = TBT2_BASE_ADDRESS; + + if (m_cfg->TcssItbtPcie3En) + m_cfg->VtdBaseAddress[VTD_TBT3] = TBT3_BASE_ADDRESS; + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); /* Skip CPU replacement check */ -- cgit v1.2.3