From ceefc74f01bcfe070477107d0677acf6b9d9c372 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 7 Feb 2022 15:27:27 +0100 Subject: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to configure the PCI MMCONF base address. Signed-off-by: Felix Held Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/sabrina/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 43c96c0c5d..239a0e800f 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -59,7 +59,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct -- cgit v1.2.3