From ce60fb1d6305744ea7655c57b1c1efbf8451a6bc Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 18 Jan 2024 20:42:54 +0100 Subject: soc/amd: factor out non-CAR romstage to common code Since the romstage code is very similar between all AMD non-CAR SoCs, factor out a common romstage implementation. All SoCs that select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so this Kconfig option can be used to determine whether to make that call. In the FSP case, amd_fsp_early_init gets called, while in the case of an implementation that doesn't rely on an FSP to do the initialization, cbmem_initialize_empty gets called to set up CBMEM which otherwise would be done inside the FSP driver code. Since only some SoCs call fch_disable_legacy_dma_io again in romstage right after amd_fsp_early_init, introduce the new SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the SoCs can specify if this call is needed or not. Signed-off-by: Felix Held Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/cezanne/Kconfig | 1 + src/soc/amd/cezanne/Makefile.inc | 1 - src/soc/amd/cezanne/romstage.c | 28 ----------------- src/soc/amd/common/block/cpu/Kconfig | 6 ++++ src/soc/amd/common/block/cpu/noncar/Makefile.inc | 1 + src/soc/amd/common/block/cpu/noncar/romstage.c | 39 ++++++++++++++++++++++++ src/soc/amd/genoa_poc/Makefile.inc | 2 -- src/soc/amd/genoa_poc/romstage.c | 16 ---------- src/soc/amd/glinda/Kconfig | 1 + src/soc/amd/glinda/Makefile.inc | 1 - src/soc/amd/glinda/romstage.c | 28 ----------------- src/soc/amd/mendocino/Kconfig | 1 + src/soc/amd/mendocino/Makefile.inc | 1 - src/soc/amd/mendocino/romstage.c | 32 ------------------- src/soc/amd/phoenix/Kconfig | 1 + src/soc/amd/phoenix/Makefile.inc | 1 - src/soc/amd/phoenix/romstage.c | 28 ----------------- src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/picasso/romstage.c | 26 ---------------- 19 files changed, 50 insertions(+), 165 deletions(-) delete mode 100644 src/soc/amd/cezanne/romstage.c create mode 100644 src/soc/amd/common/block/cpu/noncar/romstage.c delete mode 100644 src/soc/amd/genoa_poc/romstage.c delete mode 100644 src/soc/amd/glinda/romstage.c delete mode 100644 src/soc/amd/mendocino/romstage.c delete mode 100644 src/soc/amd/phoenix/romstage.c delete mode 100644 src/soc/amd/picasso/romstage.c diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 42a7bf335e..0ef658c10f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -77,6 +77,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_BLOCK_XHCI + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING select USE_DDR4 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 044d33ead2..dedf98c4bd 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += early_fch.c bootblock-y += espi_util.c romstage-y += fsp_m_params.c -romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c deleted file mode 100644 index 6b84728ad1..0000000000 --- a/src/soc/amd/cezanne/romstage.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - amd_fsp_early_init(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 1ffaece9dd..3dc90ac3b2 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -38,6 +38,12 @@ config ACPI_CPU_STRING string default "C%03X" +config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP + bool + help + Disable the legacy DMA decodes again after the call into the + reference code in romstage to fix up things. + endif # SOC_AMD_COMMON_BLOCK_NONCAR config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index f8ca357c40..f3ada6250f 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += pre_c.S bootblock-y += write_resume_eip.c bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock_measure.c romstage-y += memmap.c +romstage-y += romstage.c ramstage-y += cpu.c romstage-y += cpu.c ramstage-y += memmap.c diff --git a/src/soc/amd/common/block/cpu/noncar/romstage.c b/src/soc/amd/common/block/cpu/noncar/romstage.c new file mode 100644 index 0000000000..1ce692d568 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __noreturn romstage_main(void) +{ + post_code(POSTCODE_ROMSTAGE_MAIN); + + if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) + write_stb_to_console(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE)) { + /* Snapshot chipset state prior to any reference code call. */ + fill_chipset_state(); + } + + if (CONFIG(PLATFORM_USES_FSP2_0)) { + amd_fsp_early_init(); + } else { + cbmem_initialize_empty(); + } + + if (CONFIG(SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP)) { + /* Fix up settings the reference code should not be changing */ + fch_disable_legacy_dma_io(); + } + + memmap_stash_early_dram_usage(); + + run_ramstage(); +} diff --git a/src/soc/amd/genoa_poc/Makefile.inc b/src/soc/amd/genoa_poc/Makefile.inc index 7d54254436..01bbe7b8f9 100644 --- a/src/soc/amd/genoa_poc/Makefile.inc +++ b/src/soc/amd/genoa_poc/Makefile.inc @@ -11,8 +11,6 @@ all-y += uart.c bootblock-y += early_fch.c bootblock-y += aoac.c -romstage-y += romstage.c - ramstage-y += acpi.c ramstage-y += aoac.c ramstage-y += chip.c diff --git a/src/soc/amd/genoa_poc/romstage.c b/src/soc/amd/genoa_poc/romstage.c deleted file mode 100644 index 66a2140c07..0000000000 --- a/src/soc/amd/genoa_poc/romstage.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - cbmem_initialize_empty(); - memmap_stash_early_dram_usage(); - run_ramstage(); -} diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index b9760489d3..d3194a2412 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -78,6 +78,7 @@ config SOC_AMD_GLINDA select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PRELOAD_FSPS + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING select USE_DDR5 diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 675712f6b4..bc217d36d1 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -22,7 +22,6 @@ bootblock-y += espi_util.c verstage-y += espi_util.c romstage-y += fsp_m_params.c -romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c deleted file mode 100644 index 6b84728ad1..0000000000 --- a/src/soc/amd/glinda/romstage.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - amd_fsp_early_init(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 7192106922..194b775bb0 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -84,6 +84,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING select USE_DDR5 diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 6cb098f78b..5b9216e638 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -19,7 +19,6 @@ bootblock-y += espi_util.c verstage-y += espi_util.c romstage-y += fsp_m_params.c -romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c deleted file mode 100644 index f1ee595c84..0000000000 --- a/src/soc/amd/mendocino/romstage.c +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) - write_stb_to_console(); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - amd_fsp_early_init(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 5bfb5b9a2b..fd40231827 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -72,6 +72,7 @@ config SOC_AMD_PHOENIX_BASE select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_BLOCK_XHCI + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select USE_DDR5 select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 0301cdc0ed..82ce54d91e 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -22,7 +22,6 @@ bootblock-y += espi_util.c verstage-y += espi_util.c romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c -romstage-y += romstage.c romstage-y += soc_util.c ramstage-y += acpi.c diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c deleted file mode 100644 index 6b84728ad1..0000000000 --- a/src/soc/amd/phoenix/romstage.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - amd_fsp_early_init(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7ca25d0a39..ba58c9178b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -17,7 +17,6 @@ all_x86-y += uart.c bootblock-y += early_fch.c romstage-y += fsp_m_params.c -romstage-y += romstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c deleted file mode 100644 index 5159061b9a..0000000000 --- a/src/soc/amd/picasso/romstage.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call. */ - fill_chipset_state(); - - amd_fsp_early_init(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} -- cgit v1.2.3