From ce23d4c6f179358bf84cbdfa678d0435ae3b4cbe Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 4 Jun 2018 10:05:07 +0530 Subject: soc/intel/skylake: Add option to skip coreboot MP init This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization. Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/26818 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/google/chell/devicetree.cb | 1 - src/mainboard/google/eve/devicetree.cb | 1 - src/mainboard/google/fizz/devicetree.cb | 1 - src/mainboard/google/glados/devicetree.cb | 1 - src/mainboard/google/lars/devicetree.cb | 1 - src/mainboard/google/poppy/variants/atlas/devicetree.cb | 1 - src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nami/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 1 - src/mainboard/google/poppy/variants/soraka/devicetree.cb | 1 - src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb | 2 -- src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb | 2 -- src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb | 2 -- src/mainboard/intel/kunimitsu/devicetree.cb | 2 -- src/mainboard/intel/saddlebrook/devicetree.cb | 3 ++- src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb | 1 - src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 1 - src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/skylake/chip.h | 7 ++++++- src/soc/intel/skylake/chip_fsp20.c | 2 +- 21 files changed, 10 insertions(+), 25 deletions(-) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 2f077539a9..fa1fde4d94 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -48,7 +48,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index b42acbb8fd..fa12d8b06d 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -44,7 +44,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 45b2736b1a..6418c7ddc1 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -79,7 +79,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 94d9e53eb2..19c9beb7f4 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -48,7 +48,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 344d4b72a7..c860569c9b 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "FspSkipMpInit" = "1" register "PmTimerDisabled" = "1" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 8ae9b058e7..64e7113adc 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index eb45dbd4ce..8ea5c2da2b 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 5e2575ff5a..0c4a8e8802 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -50,7 +50,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 2c004c5a36..7cf764e755 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 91e8b46cf1..78edcc9faf 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8e6f95213d..af962881d8 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index a8e835e95c..8751255076 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -131,8 +131,6 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root ports. # PCIE Port 1 x4 -> SLOT1 register "PcieRpEnable[0]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb index 5c41f22d8a..f07d38199f 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -132,8 +132,6 @@ chip soc/intel/skylake .voltage_limit = 0x0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root ports. register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb index 2a2d761af1..0057a288a4 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb @@ -128,8 +128,6 @@ chip soc/intel/skylake .voltage_limit = 0x0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root port. register "PcieRpEnable[3]" = "1" register "PcieRpEnable[4]" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index aec57b1ffa..44aa325bff 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -141,8 +141,6 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root port 1 and 5. register "PcieRpEnable[0]" = "1" register "PcieRpEnable[4]" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 6da73dc412..43d14ede49 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -142,7 +142,8 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - register "FspSkipMpInit" = "0" + # Skip coreboot MP Init + register "use_fsp_mp_init" = "1" # Enable x1 slot register "PcieRpEnable[7]" = "1" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 1351741f90..5f61d346a8 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -62,7 +62,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 021f08ad0c..520736ced1 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -62,7 +62,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "FspSkipMpInit" = "1" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1e3fdc6fd2..9fe19d8f9b 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -171,7 +171,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; - params->SkipMpInit = config->FspSkipMpInit; + params->SkipMpInit = !config->use_fsp_mp_init; for (i = 0; i < ARRAY_SIZE(config->i2c); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2523554613..8b98662b1e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -434,7 +434,12 @@ struct soc_intel_skylake_config { SERIAL_IRQ_FRAME_PULSE_8CLK = 2, } SerialIrqConfigStartFramePulse; - u8 FspSkipMpInit; + /* + * Option for mainboard to skip coreboot MP initialization + * 0 = Make use of coreboot MP Init + * 1 = Make use of FSP MP Init + */ + u8 use_fsp_mp_init; /* * VrConfig Settings for 5 domains diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 0ba70e08ab..227e244224 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -387,7 +387,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode; - params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit; + params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init; for (i = 0; i < ARRAY_SIZE(config->i2c); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; -- cgit v1.2.3