From cdabc407cde7a7ccea46390b8ed0cfb7b95c826b Mon Sep 17 00:00:00 2001 From: John Su Date: Mon, 10 Feb 2020 13:59:27 +0800 Subject: mb/google/drallion: Set cpu_pl2_4_cfg to baseline for Drallion Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg. BUG=b:148912093 BRANCH=None TEST=build coreboot and checked IA_TDC from TAT tool. Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Mathew King --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 92f3fb9772..cdb6288173 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -65,6 +65,9 @@ chip soc/intel/cannonlake register "PchHdaIDispCodecDisconnect" = "1" register "PchHdaAudioLinkHda" = "1" + # Select CPU PL2/PL4 config + register "cpu_pl2_4_cfg" = "baseline" + # VR Settings Configuration for 2/4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- cgit v1.2.3