From ccb62960db3eff2d4c2905710ba99ba90f24bcdc Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 18 Jul 2018 11:19:40 -0700 Subject: mb/google/poppy/variants/nocturne: set nvme to use clk src 3 Latest nocturne architecture uses clk src 3 for nvme. BUG=b:111514174 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme nocturne devices are able to recognize the nvme controller. Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/27536 Reviewed-by: Lijian Zhao Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5e1b7aa41c..1d00bc2f17 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -164,13 +164,13 @@ chip soc/intel/skylake # PcieRpEnable: Enable root port # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# - # PcieRpClkSrcNumber: Uses 2 + # PcieRpClkSrcNumber: Uses 3 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" -- cgit v1.2.3