From cc93c6e47480de06ce87705a93bc46d806cabbb3 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sat, 9 Jan 2021 22:53:52 +0200
Subject: soc/amd,intel: Drop s3_resume parameter on FSP-S functions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.

Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 1 -
 src/drivers/intel/fsp1_1/ramstage.c             | 4 ++--
 src/drivers/intel/fsp2_0/include/fsp/api.h      | 4 ++--
 src/drivers/intel/fsp2_0/silicon_init.c         | 6 +++---
 src/soc/amd/cezanne/chip.c                      | 3 +--
 src/soc/amd/picasso/chip.c                      | 3 +--
 src/soc/intel/alderlake/chip.c                  | 3 +--
 src/soc/intel/alderlake/cpu.c                   | 3 +--
 src/soc/intel/apollolake/chip.c                 | 3 +--
 src/soc/intel/apollolake/cpu.c                  | 3 +--
 src/soc/intel/cannonlake/chip.c                 | 3 +--
 src/soc/intel/cannonlake/cpu.c                  | 3 +--
 src/soc/intel/denverton_ns/chip.c               | 2 +-
 src/soc/intel/elkhartlake/chip.c                | 3 +--
 src/soc/intel/elkhartlake/cpu.c                 | 3 +--
 src/soc/intel/icelake/chip.c                    | 3 +--
 src/soc/intel/icelake/cpu.c                     | 3 +--
 src/soc/intel/jasperlake/chip.c                 | 3 +--
 src/soc/intel/jasperlake/cpu.c                  | 3 +--
 src/soc/intel/quark/chip.c                      | 3 +--
 src/soc/intel/skylake/chip.c                    | 5 ++---
 src/soc/intel/tigerlake/chip.c                  | 3 +--
 src/soc/intel/tigerlake/cpu.c                   | 3 +--
 src/soc/intel/xeon_sp/cpx/chip.c                | 2 +-
 src/soc/intel/xeon_sp/skx/chip.c                | 2 +-
 25 files changed, 29 insertions(+), 48 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
index dec23938d1..d1b803e363 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -8,7 +8,6 @@
 
 /* Perform Intel silicon init. */
 void intel_silicon_init(void);
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
 /* Called after the silicon init code has run. */
 void soc_after_silicon_init(void);
 /* Initialize UPD data before SiliconInit call. */
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 34eec6e433..22d4f1c8be 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -51,7 +51,7 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
 	}
 }
 
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
+static void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header)
 {
 	FSP_SILICON_INIT fsp_silicon_init;
 	SILICON_INIT_UPD *original_params;
@@ -179,7 +179,7 @@ static void fsp_load(void)
 void intel_silicon_init(void)
 {
 	fsp_load();
-	fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3());
+	fsp_run_silicon_init(fsp_get_fih());
 }
 
 /* Initialize the UPD parameters for SiliconInit */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 63018c58db..8561600714 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -33,7 +33,7 @@ enum fsp_notify_phase {
 
 /* Main FSP stages */
 void fsp_memory_init(bool s3wake);
-void fsp_silicon_init(bool s3wake);
+void fsp_silicon_init(void);
 void fsp_temp_ram_exit(void);
 
 /*
@@ -41,7 +41,7 @@ void fsp_temp_ram_exit(void);
  * separately from calling silicon init. It might be required in cases where
  * stage cache is no longer available by the point SoC calls into silicon init.
  */
-void fsps_load(bool s3wake);
+void fsps_load(void);
 
 /* Callbacks for updating stage-specific parameters */
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 270a872965..6a2a73dbb9 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -191,7 +191,7 @@ static int fsps_get_dest(const struct fsp_load_descriptor *fspld, void **dest,
 	return 0;
 }
 
-void fsps_load(bool s3wake)
+void fsps_load(void)
 {
 	struct fsp_load_descriptor fspld = {
 		.fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS),
@@ -220,9 +220,9 @@ void fsps_load(bool s3wake)
 	load_done = 1;
 }
 
-void fsp_silicon_init(bool s3wake)
+void fsp_silicon_init(void)
 {
-	fsps_load(s3wake);
+	fsps_load();
 	do_silicon_init(&fsps_hdr);
 }
 
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index f6cac149f4..accd3e9871 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi.h>
 #include <device/device.h>
 #include <fsp/api.h>
 #include <soc/southbridge.h>
@@ -27,7 +26,7 @@ static void enable_dev(struct device *dev)
 
 static void soc_init(void *chip_info)
 {
-	fsp_silicon_init(acpi_is_wakeup_s3());
+	fsp_silicon_init();
 
 	fch_init(chip_info);
 }
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 17c7bd58e3..8722d57b7d 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -102,7 +101,7 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
 
-	fsp_silicon_init(acpi_is_wakeup_s3());
+	fsp_silicon_init();
 
 	data_fabric_set_mmio_np();
 	fch_init(chip_info);
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index c7e3fb8c2f..95ad8657ab 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -10,7 +10,6 @@
 #include <intelblocks/itss.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
@@ -134,7 +133,7 @@ void soc_init_pre_device(void *chip_info)
 	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 9fab277781..32f5ea23a4 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -19,7 +19,6 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -27,7 +26,7 @@
 
 static void soc_fsp_load(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	fsps_load();
 }
 
 static void configure_misc(void)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 39d9be5a84..7172231c07 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -23,7 +23,6 @@
 #include <intelblocks/gpio.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/pmclib.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/heci.h>
 #include <soc/intel/common/vbt.h>
@@ -302,7 +301,7 @@ static void soc_init(void *data)
 	 */
 	gpi_clear_int_cfg();
 
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	/* Restore GPIO IRQ polarities back to previous settings. */
 	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 0ae170b44d..a071337f9f 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -24,7 +24,6 @@
 #include <intelblocks/msr.h>
 #include <intelblocks/sgx.h>
 #include <reg_script.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -140,7 +139,7 @@ static struct smm_relocation_attrs relo_attrs;
 static void pre_mp_init(void)
 {
 	if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
-		fsps_load(romstage_handoff_is_resume());
+		fsps_load();
 		return;
 	}
 	x86_setup_mtrrs_with_detect();
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0958aace02..4f467a1ab7 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -10,7 +10,6 @@
 #include <intelblocks/itss.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/gpio.h>
 #include <soc/pci_devs.h>
@@ -171,7 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
 void soc_init_pre_device(void *chip_info)
 {
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index f4b72abe75..6a4f77371b 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -10,7 +10,6 @@
 #include <cpu/intel/turbo.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -23,7 +22,7 @@
 
 static void soc_fsp_load(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	fsps_load();
 }
 
 static void configure_misc(void)
diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c
index 9cf3bfb54a..77ad8e7ddc 100644
--- a/src/soc/intel/denverton_ns/chip.c
+++ b/src/soc/intel/denverton_ns/chip.c
@@ -43,7 +43,7 @@ static void soc_enable_dev(struct device *dev)
 
 static void soc_init(void *data)
 {
-	fsp_silicon_init(false);
+	fsp_silicon_init();
 	soc_save_dimm_info();
 }
 
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index 359aa11c07..001a6e1731 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -10,7 +10,6 @@
 #include <intelblocks/itss.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
@@ -122,7 +121,7 @@ void soc_init_pre_device(void *chip_info)
 	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index d0fa019ef8..984f7f2978 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -13,7 +13,6 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
 
 static void soc_fsp_load(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	fsps_load();
 }
 
 static void configure_misc(void)
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index d493f81bba..134d7cf214 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -9,7 +9,6 @@
 #include <intelblocks/gpio.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
@@ -112,7 +111,7 @@ void soc_init_pre_device(void *chip_info)
 	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index 1734ba6c30..dd70c85e11 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -13,7 +13,6 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
 
 static void soc_fsp_load(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	fsps_load();
 }
 
 static void configure_misc(void)
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index 1f58f84c18..ce4004db89 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -10,7 +10,6 @@
 #include <intelblocks/itss.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
@@ -128,7 +127,7 @@ void soc_init_pre_device(void *chip_info)
 	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 6518945d8d..a3790e11cf 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -13,7 +13,6 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
 
 static void soc_fsp_load(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	fsps_load();
 }
 
 static void configure_misc(void)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 33033a98b6..e613ced2cd 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -2,7 +2,6 @@
 
 #include <assert.h>
 #include <device/device.h>
-#include <romstage_handoff.h>
 #include <soc/ramstage.h>
 #include <soc/reg_access.h>
 
@@ -103,7 +102,7 @@ static void chip_init(void *chip_info)
 			| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
 
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 }
 
 static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index cb0fa2a6b9..4f120bc19d 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -18,7 +18,6 @@
 #include <intelblocks/xdci.h>
 #include <intelblocks/p2sb.h>
 #include <intelpch/lockdown.h>
-#include <romstage_handoff.h>
 #include <soc/acpi.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/interrupt.h>
@@ -56,7 +55,7 @@ void soc_init_pre_device(void *chip_info)
 	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	/*
 	 * Keep the P2SB device visible so it and the other devices are
@@ -77,7 +76,7 @@ void soc_init_pre_device(void *chip_info)
 
 void soc_fsp_load(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	fsps_load();
 }
 
 static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index f07cc58c95..8be04b6624 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -11,7 +11,6 @@
 #include <intelblocks/itss.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
@@ -134,7 +133,7 @@ void soc_init_pre_device(void *chip_info)
 	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
 	/* Perform silicon specific init. */
-	fsp_silicon_init(romstage_handoff_is_resume());
+	fsp_silicon_init();
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index 36dfa1b738..974401f13c 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -19,7 +19,6 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -27,7 +26,7 @@
 
 static void soc_fsp_load(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	fsps_load();
 }
 
 static void configure_misc(void)
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 778d277a0c..2c731da797 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -91,7 +91,7 @@ static void chip_final(void *data)
 static void chip_init(void *data)
 {
 	printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
-	fsp_silicon_init(false);
+	fsp_silicon_init();
 	override_hpet_ioapic_bdf();
 	pch_enable_ioapic();
 	pch_lock_dmictl();
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 4d50a25236..92f2afa099 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -59,7 +59,7 @@ static void soc_enable_dev(struct device *dev)
 static void soc_init(void *data)
 {
 	printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
-	fsp_silicon_init(false);
+	fsp_silicon_init();
 	override_hpet_ioapic_bdf();
 	pch_lock_dmictl();
 }
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