From cb92d28d7a22811f5399c589e5b231508ff42370 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 21 Mar 2024 08:05:03 +0100 Subject: soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs. TEST=intel/archercity CRB Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370 Tested-by: build bot (Jenkins) Reviewed-by: Jincheng Li Reviewed-by: Shuo Liu --- src/soc/intel/xeon_sp/ebg/Makefile.mk | 2 +- src/soc/intel/xeon_sp/ebg/include/soc/xhci.h | 53 ++++++++++++++++++++++++ src/soc/intel/xeon_sp/ebg/soc_xhci.c | 45 ++++++++++++++++++++ src/soc/intel/xeon_sp/spr/Makefile.mk | 2 +- src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h | 3 -- src/soc/intel/xeon_sp/spr/include/soc/xhci.h | 53 ------------------------ src/soc/intel/xeon_sp/spr/xhci.c | 42 ------------------- 7 files changed, 100 insertions(+), 100 deletions(-) create mode 100644 src/soc/intel/xeon_sp/ebg/include/soc/xhci.h create mode 100644 src/soc/intel/xeon_sp/ebg/soc_xhci.c delete mode 100644 src/soc/intel/xeon_sp/spr/include/soc/xhci.h delete mode 100644 src/soc/intel/xeon_sp/spr/xhci.c diff --git a/src/soc/intel/xeon_sp/ebg/Makefile.mk b/src/soc/intel/xeon_sp/ebg/Makefile.mk index ac73acbde9..b05c05bbb3 100644 --- a/src/soc/intel/xeon_sp/ebg/Makefile.mk +++ b/src/soc/intel/xeon_sp/ebg/Makefile.mk @@ -2,6 +2,6 @@ bootblock-y += soc_gpio.c soc_pch.c romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c -ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c +ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h new file mode 100644 index 0000000000..005a8e1b0b --- /dev/null +++ b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _XHCI_H_ +#define _XHCI_H_ + +#include + +#define USB2_OC_PIN_0 0x90A4 +#define USB2_OC_PIN_1 0x90A8 +#define USB2_OC_PIN_2 0x90AC +#define USB2_OC_PIN_3 0x90B0 +#define USB2_OC_PIN_4 0x90B4 +#define USB2_OC_PIN_5 0x90B8 +#define USB2_OC_PIN_6 0x90BC +#define USB2_OC_PIN_7 0x90C0 + +#define USB3_OC_PIN_0 0x9124 +#define USB3_OC_PIN_1 0x9128 +#define USB3_OC_PIN_2 0x912C +#define USB3_OC_PIN_3 0x9130 +#define USB3_OC_PIN_4 0x9134 +#define USB3_OC_PIN_5 0x9138 +#define USB3_OC_PIN_6 0x913C +#define USB3_OC_PIN_7 0x9140 + +#define USB_PORT_0 BIT(0) +#define USB_PORT_1 BIT(1) +#define USB_PORT_2 BIT(2) +#define USB_PORT_3 BIT(3) +#define USB_PORT_4 BIT(4) +#define USB_PORT_5 BIT(5) +#define USB_PORT_6 BIT(6) +#define USB_PORT_7 BIT(7) +#define USB_PORT_8 BIT(8) +#define USB_PORT_9 BIT(9) +#define USB_PORT_10 BIT(10) +#define USB_PORT_11 BIT(11) +#define USB_PORT_12 BIT(12) +#define USB_PORT_13 BIT(13) +#define USB_PORT_14 BIT(14) +#define USB_PORT_15 BIT(15) +#define USB_PORT_NONE 0 +#define OCCFGDONE BIT(31) + +struct usb_oc_mapping { + uint32_t pin; + uint32_t port; +}; + +void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins); +void lock_oc_cfg(bool lock); + +#endif /* _XHCI_H_ */ diff --git a/src/soc/intel/xeon_sp/ebg/soc_xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c new file mode 100644 index 0000000000..f8aa37b88d --- /dev/null +++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +// XHCI register +#define SYS_BUS_CFG2 0x44 + +static uint8_t *get_xhci_bar(void) +{ + const struct resource *res; + res = probe_resource(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "XHCI BAR is not found\n"); + return NULL; + } + return (void *)(uintptr_t)res->base; +} + +void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins) +{ + uint8_t *mbar = get_xhci_bar(); + uint8_t i; + + if (mbar == NULL) { + printk(BIOS_ERR, "XHCI BAR is invalid, skip USB OC mapping configuration\n"); + return; + } + for (i = 0; i < pins; i++) + write32(mbar + config[i].pin, config[i].port); +} + +void lock_oc_cfg(bool lock) +{ + uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2); + + if (lock) + cfg |= OCCFGDONE; + else + cfg &= ~(OCCFGDONE); + pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg); +} diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 163b5ea94d..fc8ab1713d 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -12,7 +12,7 @@ romstage-y += romstage.c soc_util.c ddr.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c +ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c ramstage-y += crashlog.c ioat.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 09953aa76a..510a67fa6f 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -122,9 +122,6 @@ #define IIO_DFX_TSWCTL0 0x30c #define IIO_DFX_LCK_CTL 0x504 -// XHCI register -#define SYS_BUS_CFG2 0x44 - /* MSM registers */ #define MSM_BUS 0xF2 #define MSM_DEV 3 diff --git a/src/soc/intel/xeon_sp/spr/include/soc/xhci.h b/src/soc/intel/xeon_sp/spr/include/soc/xhci.h deleted file mode 100644 index 005a8e1b0b..0000000000 --- a/src/soc/intel/xeon_sp/spr/include/soc/xhci.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _XHCI_H_ -#define _XHCI_H_ - -#include - -#define USB2_OC_PIN_0 0x90A4 -#define USB2_OC_PIN_1 0x90A8 -#define USB2_OC_PIN_2 0x90AC -#define USB2_OC_PIN_3 0x90B0 -#define USB2_OC_PIN_4 0x90B4 -#define USB2_OC_PIN_5 0x90B8 -#define USB2_OC_PIN_6 0x90BC -#define USB2_OC_PIN_7 0x90C0 - -#define USB3_OC_PIN_0 0x9124 -#define USB3_OC_PIN_1 0x9128 -#define USB3_OC_PIN_2 0x912C -#define USB3_OC_PIN_3 0x9130 -#define USB3_OC_PIN_4 0x9134 -#define USB3_OC_PIN_5 0x9138 -#define USB3_OC_PIN_6 0x913C -#define USB3_OC_PIN_7 0x9140 - -#define USB_PORT_0 BIT(0) -#define USB_PORT_1 BIT(1) -#define USB_PORT_2 BIT(2) -#define USB_PORT_3 BIT(3) -#define USB_PORT_4 BIT(4) -#define USB_PORT_5 BIT(5) -#define USB_PORT_6 BIT(6) -#define USB_PORT_7 BIT(7) -#define USB_PORT_8 BIT(8) -#define USB_PORT_9 BIT(9) -#define USB_PORT_10 BIT(10) -#define USB_PORT_11 BIT(11) -#define USB_PORT_12 BIT(12) -#define USB_PORT_13 BIT(13) -#define USB_PORT_14 BIT(14) -#define USB_PORT_15 BIT(15) -#define USB_PORT_NONE 0 -#define OCCFGDONE BIT(31) - -struct usb_oc_mapping { - uint32_t pin; - uint32_t port; -}; - -void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins); -void lock_oc_cfg(bool lock); - -#endif /* _XHCI_H_ */ diff --git a/src/soc/intel/xeon_sp/spr/xhci.c b/src/soc/intel/xeon_sp/spr/xhci.c deleted file mode 100644 index 544ea16ba9..0000000000 --- a/src/soc/intel/xeon_sp/spr/xhci.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -static uint8_t *get_xhci_bar(void) -{ - const struct resource *res; - res = probe_resource(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0); - if (!res) { - printk(BIOS_ERR, "XHCI BAR is not found\n"); - return NULL; - } - return (void *)(uintptr_t)res->base; -} - -void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins) -{ - uint8_t *mbar = get_xhci_bar(); - uint8_t i; - - if (mbar == NULL) { - printk(BIOS_ERR, "XHCI BAR is invalid, skip USB OC mapping configuration\n"); - return; - } - for (i = 0; i < pins; i++) - write32(mbar + config[i].pin, config[i].port); -} - -void lock_oc_cfg(bool lock) -{ - uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2); - - if (lock) - cfg |= OCCFGDONE; - else - cfg &= ~(OCCFGDONE); - pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg); -} -- cgit v1.2.3