From ca71e135bc68f9817c48da6393625c2cf93a2637 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 15 Jan 2021 05:06:35 +0200 Subject: soc/intel: Remove duplicate call to acpi_wake_source() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With SOC_INTEL_COMMON_BLOCK_ACPI=y the call was made twice, possibly in the order: common/block/acpi.c: acpi_wake_source() common/acpi_wake_source.c: acpi_wake_source() In this order later call would reset pm1i and gpei in GNVS. Remove the implementation in block/acpi.c and rename existing acpi_wake_source.c to block/acpi_wake_source.c. Change-Id: I74fdae63111e3ea09000d888a918ebe70d711801 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49880 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/soc/intel/braswell/ramstage.c | 2 +- src/soc/intel/common/Makefile.inc | 1 - src/soc/intel/common/acpi.h | 19 ----- src/soc/intel/common/acpi_wake_source.c | 84 ---------------------- src/soc/intel/common/block/acpi/Makefile.inc | 1 + src/soc/intel/common/block/acpi/acpi.c | 73 +------------------ src/soc/intel/common/block/acpi/acpi_wake_source.c | 78 ++++++++++++++++++++ .../block/include/intelblocks/acpi_wake_source.h | 19 +++++ src/soc/intel/denverton_ns/include/soc/nvs.h | 2 +- src/soc/intel/skylake/acpi.c | 2 +- 10 files changed, 103 insertions(+), 178 deletions(-) delete mode 100644 src/soc/intel/common/acpi.h delete mode 100644 src/soc/intel/common/acpi_wake_source.c create mode 100644 src/soc/intel/common/block/acpi/acpi_wake_source.c create mode 100644 src/soc/intel/common/block/include/intelblocks/acpi_wake_source.h diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 1a77b80f1e..e59f3eb886 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -18,7 +19,6 @@ #include #include #include -#include #include #define SHOW_PATTRS 1 diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 9993bceedf..56e3336fd7 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -17,7 +17,6 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += hda_verb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-$(CONFIG_MMA) += mma.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h deleted file mode 100644 index efa0336f47..0000000000 --- a/src/soc/intel/common/acpi.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _INTEL_COMMON_ACPI_H_ -#define _INTEL_COMMON_ACPI_H_ - -#include - -/* - * SOC specific handler to provide the wake source data for ACPI _SWS. - * - * @pm1: PM1_STS register with only enabled events set - * @gpe0: GPE0_STS registers with only enabled events set - * - * return the number of registers in the gpe0 array or -1 if nothing - * is provided by this function. - */ -int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0); - -#endif /* _INTEL_COMMON_ACPI_H_ */ diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c deleted file mode 100644 index 5e67e2adca..0000000000 --- a/src/soc/intel/common/acpi_wake_source.c +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "acpi.h" - -__weak int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, - uint32_t **gpe0) -{ - return -1; -} - -/* Save wake source data for ACPI _SWS methods in NVS */ -static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) -{ - uint32_t pm1, *gpe0; - int gpe_reg, gpe_reg_count; - int reg_size = sizeof(uint32_t) * 8; - - gpe_reg_count = soc_fill_acpi_wake(ps, &pm1, &gpe0); - if (gpe_reg_count < 0) - return; - - /* Scan for first set bit in PM1 */ - for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) { - if (pm1 & 1) - break; - pm1 >>= 1; - } - - /* If unable to determine then return -1 */ - if (gnvs->pm1i >= 16) - gnvs->pm1i = -1; - - /* Scan for first set bit in GPE registers */ - for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) { - uint32_t gpe = gpe0[gpe_reg]; - int start = gpe_reg * reg_size; - int end = start + reg_size; - - if (gpe == 0) { - if (!gnvs->gpei) - gnvs->gpei = end; - continue; - } - - for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { - if (gpe & 1) - break; - gpe >>= 1; - } - } - - /* If unable to determine then return -1 */ - if (gnvs->gpei >= gpe_reg_count * reg_size) - gnvs->gpei = -1; - - printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", - (long long)gnvs->pm1i, (long long)gnvs->gpei); -} - -static void acpi_save_wake_source(void *unused) -{ - const struct chipset_power_state *ps; - struct global_nvs *gnvs = acpi_get_gnvs(); - if (!gnvs) - return; - - gnvs->pm1i = -1; - gnvs->gpei = -1; - - if (acpi_pm_state_for_wake(&ps) < 0) - return; - - pm_fill_gnvs(gnvs, ps); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index 4e3a323625..c605088dbe 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1,2 +1,3 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index dc98b0d636..b36f2567f3 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -204,7 +205,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, * return the number of registers in the gpe0 array */ -static int acpi_fill_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0) +int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0) { static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; @@ -438,73 +439,3 @@ void generate_cpu_entries(const struct device *device) /* Add a method to notify processor nodes */ acpigen_write_processor_cnot(num_virt); } - -/* Save wake source data for ACPI _SWS methods in NVS */ -static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) -{ - uint32_t pm1, *gpe0; - int gpe_reg, gpe_reg_count; - int reg_size = sizeof(uint32_t) * 8; - - gpe_reg_count = acpi_fill_wake(ps, &pm1, &gpe0); - if (gpe_reg_count < 0) - return; - - /* Scan for first set bit in PM1 */ - for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) { - if (pm1 & 1) - break; - pm1 >>= 1; - } - - /* If unable to determine then return -1 */ - if (gnvs->pm1i >= 16) - gnvs->pm1i = -1; - - /* Scan for first set bit in GPE registers */ - for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) { - uint32_t gpe = gpe0[gpe_reg]; - int start = gpe_reg * reg_size; - int end = start + reg_size; - - if (gpe == 0) { - if (!gnvs->gpei) - gnvs->gpei = end; - continue; - } - - for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { - if (gpe & 1) - break; - gpe >>= 1; - } - } - - /* If unable to determine then return -1 */ - if (gnvs->gpei >= gpe_reg_count * reg_size) - gnvs->gpei = -1; - - printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", - (long long)gnvs->pm1i, (long long)gnvs->gpei); -} - -static void acpi_save_wake_source(void *unused) -{ - if (!CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)) - return; - - const struct chipset_power_state *ps; - struct global_nvs *gnvs = acpi_get_gnvs(); - if (!gnvs) - return; - - gnvs->pm1i = -1; - gnvs->gpei = -1; - - if (acpi_pm_state_for_wake(&ps) < 0) - return; - - pm_fill_gnvs(gnvs, ps); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); diff --git a/src/soc/intel/common/block/acpi/acpi_wake_source.c b/src/soc/intel/common/block/acpi/acpi_wake_source.c new file mode 100644 index 0000000000..3ffcac813b --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi_wake_source.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Save wake source data for ACPI _SWS methods in NVS */ +static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) +{ + uint32_t pm1, *gpe0; + int gpe_reg, gpe_reg_count; + int reg_size = sizeof(uint32_t) * 8; + + gpe_reg_count = soc_fill_acpi_wake(ps, &pm1, &gpe0); + if (gpe_reg_count < 0) + return; + + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } + + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + /* Scan for first set bit in GPE registers */ + for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) { + uint32_t gpe = gpe0[gpe_reg]; + int start = gpe_reg * reg_size; + int end = start + reg_size; + + if (gpe == 0) { + if (!gnvs->gpei) + gnvs->gpei = end; + continue; + } + + for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { + if (gpe & 1) + break; + gpe >>= 1; + } + } + + /* If unable to determine then return -1 */ + if (gnvs->gpei >= gpe_reg_count * reg_size) + gnvs->gpei = -1; + + printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", + (long long)gnvs->pm1i, (long long)gnvs->gpei); +} + +static void acpi_save_wake_source(void *unused) +{ + const struct chipset_power_state *ps; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; + + gnvs->pm1i = -1; + gnvs->gpei = -1; + + if (acpi_pm_state_for_wake(&ps) < 0) + return; + + pm_fill_gnvs(gnvs, ps); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/acpi_wake_source.h b/src/soc/intel/common/block/include/intelblocks/acpi_wake_source.h new file mode 100644 index 0000000000..efa0336f47 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/acpi_wake_source.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _INTEL_COMMON_ACPI_H_ +#define _INTEL_COMMON_ACPI_H_ + +#include + +/* + * SOC specific handler to provide the wake source data for ACPI _SWS. + * + * @pm1: PM1_STS register with only enabled events set + * @gpe0: GPE0_STS registers with only enabled events set + * + * return the number of registers in the gpe0 array or -1 if nothing + * is provided by this function. + */ +int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0); + +#endif /* _INTEL_COMMON_ACPI_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index 017a5808e9..3dd747dbbd 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -46,7 +46,7 @@ struct __packed global_nvs { u32 tsegb; /* 0x54 - TSEG Base Low */ u32 tsegl; /* 0x58 - TSEG Length/Size */ - /* Just to satisfy common/block/acpi/acpi.c. */ + /* Required for future unified acpi_save_wake_source. */ u32 pm1i; u32 gpei; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index d62960dbe2..e1e950b376 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -12,12 +12,12 @@ #include #include #include +#include #include #include #include #include #include -#include #include #include #include -- cgit v1.2.3