From c8c648f111b51b7360e24308caad7bfa19cc8589 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Fri, 27 May 2022 15:45:03 +1000 Subject: mb/google/nissa: Add and default to 16 MB layout Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and make it default for nissa. BUG=b:202783191 TEST=build nissa and brya firmware, check they're still 32MB Signed-off-by: Kangheui Won Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716 Tested-by: build bot (Jenkins) Reviewed-by: Reka Norman --- src/mainboard/google/brya/Kconfig | 7 ++- src/mainboard/google/brya/Kconfig.name | 3 ++ src/mainboard/google/brya/chromeos-nissa-16MiB.fmd | 51 +++++++++++++++++++ src/mainboard/google/brya/chromeos-nissa-32MiB.fmd | 59 ++++++++++++++++++++++ src/mainboard/google/brya/chromeos-nissa.fmd | 59 ---------------------- 5 files changed, 118 insertions(+), 61 deletions(-) create mode 100644 src/mainboard/google/brya/chromeos-nissa-16MiB.fmd create mode 100644 src/mainboard/google/brya/chromeos-nissa-32MiB.fmd delete mode 100644 src/mainboard/google/brya/chromeos-nissa.fmd diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 3874e6a796..cd45164fc7 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BRYA_COMMON def_bool n - select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_ALC1015 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A @@ -41,6 +40,7 @@ config BOARD_GOOGLE_BRYA_COMMON config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_GOOGLE_BRYA_COMMON + select BOARD_ROMSIZE_KB_32768 select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P @@ -50,6 +50,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n select BOARD_GOOGLE_BRYA_COMMON + select BOARD_ROMSIZE_KB_32768 select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP select HAVE_SLP_S0_GATE select MEMORY_SODIMM @@ -62,6 +63,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK config BOARD_GOOGLE_BASEBOARD_NISSA def_bool n select BOARD_GOOGLE_BRYA_COMMON + select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N @@ -132,7 +134,8 @@ config DRIVER_TPM_I2C_ADDR config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_BRASK - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384 + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-32MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_32768 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" config TPM_TIS_ACPI_INTERRUPT diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7209e368a3..62aa03878d 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -86,6 +86,7 @@ config BOARD_GOOGLE_KANO config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" select BOARD_GOOGLE_BASEBOARD_NISSA + select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA @@ -95,6 +96,7 @@ config BOARD_GOOGLE_NEREID bool "-> Nereid" select ALDERLAKE_CONFIGURE_DESCRIPTOR select BOARD_GOOGLE_BASEBOARD_NISSA + select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_GPIO_KEYS @@ -204,6 +206,7 @@ config BOARD_GOOGLE_KINOX config BOARD_GOOGLE_CRAASK bool "-> Craask" select BOARD_GOOGLE_BASEBOARD_NISSA + select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA diff --git a/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd b/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd new file mode 100644 index 0000000000..9ccea06d3f --- /dev/null +++ b/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd @@ -0,0 +1,51 @@ +FLASH 16M { + SI_ALL 3776K { + SI_DESC 4K + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1360K + CSE_DATA 420K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 1984K + } + } + SI_BIOS 12608K { + RW_SECTION_A 3668K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 1434K + } + RW_LEGACY(CBFS) 1M + RW_MISC 152K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K + } + RW_SECTION_B 3668K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 1434K + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd new file mode 100644 index 0000000000..5d386f916b --- /dev/null +++ b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd @@ -0,0 +1,59 @@ +FLASH 32M { + SI_ALL 3776K { + SI_DESC 4K + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1360K + CSE_DATA 420K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 1984K + } + } + SI_BIOS 28992K { + RW_SECTION_A 4344K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 1434K + } + RW_LEGACY(CBFS) 1M + RW_MISC 152K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K + } + # RW UNUSED Region 1. + RW_UNUSED_1 7088K + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 4344K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 1434K + } + # RW UNUSED Region 2. + RW_UNUSED_2 7944K + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/brya/chromeos-nissa.fmd b/src/mainboard/google/brya/chromeos-nissa.fmd deleted file mode 100644 index 5d386f916b..0000000000 --- a/src/mainboard/google/brya/chromeos-nissa.fmd +++ /dev/null @@ -1,59 +0,0 @@ -FLASH 32M { - SI_ALL 3776K { - SI_DESC 4K - SI_ME { - CSE_LAYOUT 8K - CSE_RO 1360K - CSE_DATA 420K - # 64-KiB aligned to optimize RW erases during CSE update. - CSE_RW 1984K - } - } - SI_BIOS 28992K { - RW_SECTION_A 4344K { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 64 - ME_RW_A(CBFS) 1434K - } - RW_LEGACY(CBFS) 1M - RW_MISC 152K { - UNIFIED_MRC_CACHE(PRESERVE) 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - } - # RW UNUSED Region 1. - RW_UNUSED_1 7088K - # This section starts at the 16M boundary in SPI flash. - # ADL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 4344K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - ME_RW_B(CBFS) 1434K - } - # RW UNUSED Region 2. - RW_UNUSED_2 7944K - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO 4M { - RO_VPD(PRESERVE) 16K - RO_GSCVD 8K - RO_SECTION { - FMAP 2K - RO_FRID 64 - GBB@4K 12K - COREBOOT(CBFS) - } - } - } -} -- cgit v1.2.3