From c896df7f158cf759906f4f164330fb552bbe0fec Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 16:16:01 +0000 Subject: mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS Signed-off-by: Mike Banon Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 4 ---- src/mainboard/jetway/nf81-t56n-lf/Kconfig.name | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 2 ++ src/mainboard/jetway/nf81-t56n-lf/bootblock.c | 27 ++++++++++++++++++++++++ src/mainboard/jetway/nf81-t56n-lf/romstage.c | 29 -------------------------- 5 files changed, 31 insertions(+), 35 deletions(-) create mode 100644 src/mainboard/jetway/nf81-t56n-lf/bootblock.c delete mode 100644 src/mainboard/jetway/nf81-t56n-lf/romstage.c diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index dfa01b93a6..d2dda6725f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_JETWAY_NF81_T56N_LF - def_bool n - if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name index 0b676274ae..2e660f937c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_JETWAY_NF81_T56N_LF -# bool"NF81_T56N_LF" +config BOARD_JETWAY_NF81_T56N_LF + bool "NF81_T56N_LF" diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index ba56286636..bf86007cec 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c new file mode 100644 index 0000000000..5ecfaf74f8 --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ +#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) + +void bootblock_mainboard_early_init(void) +{ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c deleted file mode 100644 index 5e61bddfcc..0000000000 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan . - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ -#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} -- cgit v1.2.3