From c762e231da33aeb4fbd53b15e429121d498f7b2a Mon Sep 17 00:00:00 2001
From: Caveh Jalali <caveh@chromium.org>
Date: Wed, 31 Aug 2022 16:53:59 -0700
Subject: util/spd_tools: Update LP5X support for ADL/RPL/MTL

This updates the SPD utility and generated SPDs for LP5X to use memory
type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on
Intel Tech Advisory Doc ID #616599 dated May 2022, page 15.

SPDs were regenerated with:
  "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5"

This only affects the SPDs for 2 memory parts for Intel SoCs and the
only board referencing these is rex.

BUG=b:242765117
TEST=inspected SPD hex dump

Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
---
 spd/lp5/set-0/spd-7.hex           |  2 +-
 spd/lp5/set-0/spd-8.hex           |  2 +-
 util/spd_tools/src/spd_gen/lp5.go | 17 ++++-------------
 3 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/spd/lp5/set-0/spd-7.hex b/spd/lp5/set-0/spd-7.hex
index 16c789be0f..0e475cd3eb 100644
--- a/spd/lp5/set-0/spd-7.hex
+++ b/spd/lp5/set-0/spd-7.hex
@@ -1,4 +1,4 @@
-23 10 13 0E 16 22 95 08 00 00 00 00 02 01 00 00
+23 10 15 0E 16 22 95 08 00 00 00 00 02 01 00 00
 00 00 09 00 00 00 00 00 AB 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-0/spd-8.hex b/spd/lp5/set-0/spd-8.hex
index 6a33e82c1a..b7f054f802 100644
--- a/spd/lp5/set-0/spd-8.hex
+++ b/spd/lp5/set-0/spd-8.hex
@@ -1,4 +1,4 @@
-23 10 13 0E 16 22 B5 08 00 00 00 00 0A 01 00 00
+23 10 15 0E 16 22 B5 08 00 00 00 00 0A 01 00 00
 00 00 09 00 00 00 00 00 AB 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go
index e4655cee73..bf7b8331e1 100644
--- a/util/spd_tools/src/spd_gen/lp5.go
+++ b/util/spd_tools/src/spd_gen/lp5.go
@@ -72,7 +72,6 @@ type LP5Set struct {
 	otherOptionalFeatures  byte
 	busWidthEncoding  byte
 	speedToTCKMinPs map[int]int
-	lp5xOverrideType byte
 }
 
 /* ------------------------------------------------------------------------------------------ */
@@ -214,12 +213,6 @@ var LP5SetInfo = map[int]LP5Set{
 			 6400 : 1250, /* 1 / (6400 / 2 / 4) */
 			 5500 : 1455, /* 1 / (5500 / 2 / 4) */
 		},
-
-		/*
-		 * Intel FSP code doesn't distinguish between LP5/5X, existing
-		 * SPDs have been using 0x13 for both types.
-		 */
-		lp5xOverrideType: LP5SPDValueMemoryType,
 	},
 	1: {
 		SPDRevision: LP5SPDValueRevision1_1,
@@ -245,8 +238,6 @@ var LP5SetInfo = map[int]LP5Set{
 		 * Set to 0x02.
 		 */
 		busWidthEncoding: 0x02,
-
-		lp5xOverrideType: LP5XSPDValueMemoryType,
 	},
 }
 
@@ -473,12 +464,12 @@ func LP5GetBankGroups(memAttribs *LP5MemAttributes) int {
 }
 
 func LP5EncodeMemoryType(memAttribs *LP5MemAttributes) byte {
-	var b byte = LP5SPDValueMemoryType
+	var b byte
 
 	if memAttribs.LP5X {
-		if f, ok := LP5SetInfo[LP5CurrSet]; ok {
-			b = f.lp5xOverrideType
-		}
+		b = LP5XSPDValueMemoryType
+	} else {
+		b = LP5SPDValueMemoryType
 	}
 	return b
 }
-- 
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