From c68456ee4b03051f24de3cf57cdb8e0ea1be99fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 18 Jan 2023 13:37:28 +0100 Subject: soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72072 Reviewed-by: Sean Rhodes Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 395d7aa688..1157f063d4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -64,6 +64,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE + select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B select PLATFORM_USES_FSP2_0 select PMC_INVALID_READ_AFTER_WRITE select PMC_GLOBAL_RESET_ENABLE_LOCK -- cgit v1.2.3