From c66c15334adb100eb55253cb03dbc4605becee46 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 27 May 2020 13:34:04 -0700 Subject: soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD This patch adds support for enabling/disabling PCIe hot-plug via a chip config option PcieRpHotPlug, which is copied to the corresponding FSP-S UPD. BUG=b:156879564 BRANCH=none TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled Signed-off-by: Wonkyu Kim Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794 Reviewed-by: Tim Wawrzynczak Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 1 + src/soc/intel/tigerlake/fsp_params.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 9c179693ed..30377aaf79 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -135,6 +135,7 @@ struct soc_intel_tigerlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b9dbec87f5..3fbb89a793 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -165,6 +165,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; + params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; } /* Enable ClkReqDetect for enabled port */ -- cgit v1.2.3