From c6589aefc16dc8911bc07c2fbdf2e81efe732796 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 28 Nov 2020 13:17:54 -0600 Subject: drivers/intel/gma: Include gfx.asl by default for all platforms... MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit which select INTEL_GMA_ACPI. Rework brightness level includes and platform-level asl files to avoid duplicate device definition for GFX0. Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common platforms already do. Adjust mb/51nb/x210 to prevent device redefinition. Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for the IGD to exist, even if ACPI brightness controls are not utilized. This change adds a GFX0 ACPI device for all boards whose platforms select INTEL_GMA_ACPI without requiring non-functional brightness controls to be added at the board level. Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/drivers/intel/gma/acpi/gma.asl | 4 +--- src/mainboard/51nb/x210/acpi/graphics.asl | 3 +-- src/northbridge/intel/gm45/acpi/gm45.asl | 3 +++ src/northbridge/intel/haswell/acpi/hostbridge.asl | 3 +++ src/northbridge/intel/i945/acpi/i945.asl | 1 + src/northbridge/intel/i945/acpi/igd.asl | 4 +--- src/northbridge/intel/ironlake/acpi/ironlake.asl | 3 +++ src/northbridge/intel/pineview/acpi/pineview.asl | 3 +++ src/northbridge/intel/sandybridge/acpi/sandybridge.asl | 3 +++ src/northbridge/intel/x4x/acpi/x4x.asl | 3 +++ src/soc/intel/baytrail/acpi/southcluster.asl | 3 +++ src/soc/intel/braswell/acpi/southcluster.asl | 3 +++ src/soc/intel/broadwell/acpi/hostbridge.asl | 3 +++ src/soc/intel/skylake/acpi/pch.asl | 3 +++ 14 files changed, 34 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/gma/acpi/gma.asl b/src/drivers/intel/gma/acpi/gma.asl index 03b049106c..2282110fb9 100644 --- a/src/drivers/intel/gma/acpi/gma.asl +++ b/src/drivers/intel/gma/acpi/gma.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) - OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) Field (GFXC, DWordAcc, NoLock, Preserve) { diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl index e703ba1936..e57753888c 100644 --- a/src/mainboard/51nb/x210/acpi/graphics.asl +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) Method (_DOS, 1, NotSerialized) { /* We never do anything in firmware, so _DOS is a noop */ diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index e4d8d66993..f13133d6ef 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -33,3 +33,6 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" + +// Integrated graphics 0:2.0 +#include diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 28a33d842c..a930afe875 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -204,3 +204,6 @@ Device (PDRC) /* PCI Express Graphics */ #include "peg.asl" #endif + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index cdc77b5fa7..c2142cc50a 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -77,4 +77,5 @@ Device (PDRC) #include "peg.asl" // Integrated graphics 0:2.0 +#include #include "igd.asl" diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 5258c52672..4fc2da2558 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) - Name (BRIG, Package (0x12) { 0xf, diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 3cf597daf7..4f9549c219 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -36,3 +36,6 @@ Device (PDRC) Return(PDRS) } } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 9515c317a9..5fb2b1233e 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -32,3 +32,6 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" + +// Integrated graphics 0:2.0 +#include diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 728d8e3ff5..1e47c1f21b 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -52,3 +52,6 @@ Device (PDRC) Return(PDRS) } } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 5a3c0b6132..b013da7814 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -30,3 +30,6 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" + +// Integrated graphics 0:2.0 +#include diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index e3997d75f7..f59f2406ef 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -256,3 +256,6 @@ Scope (\_SB.PCI0) // LPE Device #include "lpe.asl" } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 2c31d40d22..d74647e98d 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -272,3 +272,6 @@ Scope (\_SB.PCI0) /* SCC Devices */ #include "scc.asl" } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 3e7ced0296..2b44c6522f 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -195,3 +195,6 @@ Device (PDRC) /* Configurable TDP */ #include "ctdp.asl" + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 6eea5bb53a..02e30f770f 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -65,3 +65,6 @@ Method (_OSC, 4) #if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include #endif + +/* Integrated graphics 0:2.0 */ +#include -- cgit v1.2.3