From c5ac6d9ec5689e50d9b501b7cfa752ac26486b2c Mon Sep 17 00:00:00 2001 From: Malik_Hsu Date: Sat, 24 Jul 2021 18:00:44 +0800 Subject: mb/google/brya/variants/primus: Update NVMe clk According to the schematic diagram of proto, modify the clock of nvme from the baseboard default to src0. BUG=b:194487277 Signed-off-by: Malik_Hsu Change-Id: I41be517b434513bca2332ec37e54f56910302bb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/primus/overridetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 6464b8bcbf..39aa77ea9a 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -176,6 +176,14 @@ chip soc/intel/alderlake device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE9-12 SSD device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- cgit v1.2.3