From c3d74273a748c0cfc78b258369451c35c122372b Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 25 Aug 2016 15:44:39 -0500 Subject: mainboard/google/reef: set SLP_S3_L assertion width to 28ms The reef board needs at least ~28ms for its S0 rails to discharge when S3 is entered. Because of the granularity in the chipset the effective SLP_S3_L assertion width is 50ms. BUG=chrome-os-partner:56581 Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/16327 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Paul Menzel --- src/mainboard/google/reef/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index a877e863bf..4d08fae834 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -50,6 +50,9 @@ chip soc/intel/apollolake # Enable I2C2 bus early for TPM access register "i2c[2].early_init" = "1" + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF -- cgit v1.2.3