From bf50c31184d457c24f66b339cd28f84cbdd4177f Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Mon, 21 Dec 2020 14:55:38 -0800 Subject: soc/intel/tgl: Add configurable value for UsbTcPortEn As a requirement of TCSS this setting needs to be correctly set to determine what Type-C ports are enabled on the platform. Without this value correctly set there can be adverse effects on the other TCSS specific values. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that S0ix cycles no longer fail when the IomPortPad is set to 0 Change-Id: I6c5260cda71041439fe89d15bd3cafd4052ef1e7 Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/48813 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Caveh Jalali --- src/soc/intel/tigerlake/chip.h | 7 +++++++ src/soc/intel/tigerlake/fsp_params.c | 1 + 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f38330b988..86e77da972 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -327,6 +327,13 @@ struct soc_intel_tigerlake_config { uint8_t TcssXhciEn; uint8_t TcssXdciEn; + /* + * Specifies which Type-C Ports are enabled on the system + * each bit represents a port starting at 0 + * Example: set value to 0x3 for ports 0 and 1 to be enabled + */ + uint8_t UsbTcPortEn; + /* * IOM Port Config * If a port orientation needs to be controlled by the SOC this setting must be diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b31d0acb04..c0d712ca35 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -123,6 +123,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->D3ColdEnable = !config->TcssD3ColdDisable; + params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; -- cgit v1.2.3