From bd8e761be20c08e56fd79e357727101def0ff622 Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Wed, 24 Jun 2020 18:29:06 -0700 Subject: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry This is a W/A to avoid a communication issue with CSE Lite over Heci interface. This will help to avoid boot failures with CSE Lite until the permanent fix is available. BUG=b:159884143 TEST=build and boot volteer with serial and non-serial image Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685 Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cse/cse_lite.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 3077c7f09e..8e43e35c47 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -361,4 +361,8 @@ void cse_fw_sync(void *unused) } } +#if CONFIG(SOC_INTEL_TIGERLAKE) +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL); +#else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); +#endif -- cgit v1.2.3