From bc8762eaef571da9f4681d09a8ec6d2a501a8115 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 25 Apr 2018 15:50:27 +0200 Subject: src: Fix a typo on "mtrr" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change "mttrs" to mtrrs. Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/25823 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Martin Roth --- src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 +- src/soc/intel/baytrail/romstage/romstage.c | 8 ++++---- src/soc/intel/broadwell/include/soc/romstage.h | 2 +- src/soc/intel/broadwell/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/stack.c | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 892a653769..d79be7089c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -54,7 +54,7 @@ struct romstage_params { * 16. src/soc/intel/common/romstage.c/romstage_common - return * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return * 18. src/soc/intel/common/romstage.c/romstage_main - return - * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs + * 19. src/soc/intel/common/stack.c/setup_stack_and_mtrrs * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup * after call to romstage_main * 21. FSP binary/TempRamExit diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 0e8710a903..980064c2b0 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -50,7 +50,7 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void *setup_stack_and_mttrs(void); +static void *setup_stack_and_mtrrs(void); static void program_base_addresses(void) { @@ -131,7 +131,7 @@ void * asmlinkage romstage_main(unsigned long bist, /* Call into mainboard. */ mainboard_romstage_entry(&rp); - return setup_stack_and_mttrs(); + return setup_stack_and_mtrrs(); } static struct chipset_power_state power_state CAR_GLOBAL; @@ -248,9 +248,9 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* setup_stack_and_mttrs() determines the stack to use after +/* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void *setup_stack_and_mttrs(void) +static void *setup_stack_and_mtrrs(void) { int num_mtrrs; uint32_t *slot; diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index eb4e097f00..e52004bfd5 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -33,7 +33,7 @@ asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo, uint32_t tsc_high); asmlinkage void romstage_after_car(void); void raminit(struct pei_data *pei_data); -void *setup_stack_and_mttrs(void); +void *setup_stack_and_mtrrs(void); struct chipset_power_state; struct chipset_power_state *fill_power_state(void); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 025855b47b..8a3f2911a0 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -80,7 +80,7 @@ asmlinkage void *romstage_main(unsigned long bist, /* Call into mainboard. */ mainboard_romstage_entry(&rp); - return setup_stack_and_mttrs(); + return setup_stack_and_mtrrs(); } /* Entry from the mainboard. */ diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index a6a4b4bfc9..aa36e29ccf 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -30,9 +30,9 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) return stack; } -/* setup_stack_and_mttrs() determines the stack to use after +/* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mttrs(void) +void *setup_stack_and_mtrrs(void) { int num_mtrrs; uint32_t *slot; -- cgit v1.2.3