From bbed4d9ff0adf1914cf0af15dd430a7c91f638bd Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 28 Aug 2020 02:09:29 +0200 Subject: mb/amd/mandolin: move PCIe GPP clock setting to devicetree Checked with the schematics that all PCIe clocks have a corresponding clock enable pin. BUG=b:149970243 BRANCH=zork Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 0004ecd266..c6031302cc 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -115,6 +115,15 @@ chip soc/amd/picasso .flash_ch_en = 0, }" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" + register "gpp_clk_config[5]" = "GPP_CLK_REQ" + register "gpp_clk_config[6]" = "GPP_CLK_REQ" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3