From bba14fe497be6b45f570e04049f95b5908843ae5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 18 Apr 2023 18:51:38 +0200 Subject: soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register Clang complains about this. Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/74538 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/cavium/cn81xx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index 43b64d5430..9ed20d09d7 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -35,7 +35,7 @@ void secondary_cpu_init(size_t core_id) size_t cpu_self_get_core_id(void) { - u32 mpidr_el1; + u64 mpidr_el1; asm("mrs %0, MPIDR_EL1\n\t" : "=r" (mpidr_el1) :: "memory"); /* Core is 4 bits from AFF0 and rest from AFF1 */ -- cgit v1.2.3