From ba41ee1f0a74cf6b0ed0c068b6560e60f7d760eb Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Mon, 6 Apr 2020 14:42:07 -0700 Subject: mb/google/volteer: fix incorrect fields in SPDs According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16) This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD). BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel. Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Caveh Jalali --- .../volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 2 +- .../volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex index a94b41a381..94f258e1e9 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 19 95 08 00 00 00 00 02 21 00 00 +23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex index 7ef8220252..90202f983c 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- cgit v1.2.3