From b9c049a3680f82fd62637f9e4bae1d5ef67fd504 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 27 Jul 2018 15:29:21 +0200 Subject: sb/intel/i82801gx: Select INTEL_TOP_SWAP_BOOTBLOCK_SIZE This effectively means it is possible to run another bootblock located at top_of_flash - 64K. The i82801gx southbridge has the ability to swap the two top 64K ranges by flipping the BUC.TS bit (RCBA[3414] bit0). This allows coreboot to build roms with a bootblock at the top swap offset by selecting CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK. Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27748 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/southbridge/intel/i82801gx/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 7e48848c7b..fbae6452eb 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -28,6 +28,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select INTEL_HAS_TOP_SWAP if SOUTHBRIDGE_INTEL_I82801GX @@ -43,4 +44,9 @@ config HPET_MIN_TICKS hex default 0x80 +config INTEL_TOP_SWAP_BOOTBLOCK_SIZE + hex + # Always 64K, all other options are invalid + default 0x10000 + endif -- cgit v1.2.3