From b99cd85f740e15688578ab16dd5156d5709baef0 Mon Sep 17 00:00:00 2001 From: Morris Hsu Date: Fri, 31 Mar 2023 14:53:02 +0800 Subject: mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_emp Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. BUG=None TEST=build FW and check Type-A USB3 port0/port1 RX pass Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Signed-off-by: Morris Hsu Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Nick Vaccaro --- .../google/brya/variants/constitution/overridetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 67684b9891..4b894b02f8 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -22,6 +22,19 @@ chip soc/intel/alderlake register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A0 + register "usb3_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI-IN register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port A3 -- cgit v1.2.3