From b866610156f88fdb0cbe96887d6ee84567aa521c Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Mon, 1 Apr 2019 22:37:31 +0530 Subject: mb/google/hatch: Change the DEVSLP reset config to PLTRST In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device is already powered off. However on hatch the SATA power is still enabled. And, since DEVSLP is low, this causes the SATA device to not enter low power state. The fix here is to set the pad config to be reset on PLTRST assertion which will cause the pin to be high impedance state and will be pulled up by the SATA device. BUG=b:126611255 BRANCH=None TEST=Make sure that S3 and S0ix is working fine on hatch. And also make sure that DEVSLP is pulled high in S3. Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981 Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32136 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 4d1c87e02e..0391dfecb0 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -241,7 +241,7 @@ static const struct pad_config gpio_table[] = { /* E4 : M2_SSD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* E6 : M2_SSD_RST_L */ PAD_NC(GPP_E6, NONE), /* E7 : GPP_E7 ==> NC */ -- cgit v1.2.3