From b7fb24677c4adff1d7648de260c3ee9e7f5b45ee Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 26 Feb 2020 20:16:55 +0530 Subject: soc/intel/tigerlake: Add display related UPD configs for Jasper Lake TEST=Build dedede board Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_jsl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e88d809cd3..829e1e35ea 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -87,6 +87,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + /* Display */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + /* Audio */ m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0; -- cgit v1.2.3