From b759ede57940aef94f648def5ada163ec6fa166d Mon Sep 17 00:00:00 2001 From: robbie zhang Date: Mon, 27 Jul 2015 14:40:23 -0700 Subject: skylake: clean-up pei_data Remove the items that are obviously broadwell left or become no-need with fsp. BUG=chrome-os-partner:43186 BRANCH=None TEST=build and boot on sklrvp3. Signed-off-by: robbie zhang Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee Signed-off-by: Patrick Georgi Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010 Original-Reviewed-on: https://chromium-review.googlesource.com/288833 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Robbie Zhang Original-Tested-by: Robbie Zhang Reviewed-on: http://review.coreboot.org/11072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/glados/pei_data.c | 3 - src/mainboard/intel/kunimitsu/pei_data.c | 3 - src/mainboard/intel/sklrvp/pei_data.c | 3 - src/soc/intel/skylake/include/soc/iomap.h | 6 -- src/soc/intel/skylake/include/soc/pei_data.h | 96 ------------------------- src/soc/intel/skylake/include/soc/pei_wrapper.h | 19 ----- src/soc/intel/skylake/pei_data.c | 9 --- 7 files changed, 139 deletions(-) diff --git a/src/mainboard/google/glados/pei_data.c b/src/mainboard/google/glados/pei_data.c index 677ea32d0a..55d7f08aeb 100644 --- a/src/mainboard/google/glados/pei_data.c +++ b/src/mainboard/google/glados/pei_data.c @@ -43,9 +43,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; pei_data->ec_present = 1; - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c index e8d75622e9..af9462f590 100644 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ b/src/mainboard/intel/kunimitsu/pei_data.c @@ -43,9 +43,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; pei_data->ec_present = 1; - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/intel/sklrvp/pei_data.c b/src/mainboard/intel/sklrvp/pei_data.c index 6c42f28a14..b5302b9294 100644 --- a/src/mainboard/intel/sklrvp/pei_data.c +++ b/src/mainboard/intel/sklrvp/pei_data.c @@ -45,9 +45,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; pei_data->ec_present = 1; - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 920b6f6655..c478dafead 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -60,10 +60,4 @@ #define SMBUS_BASE_ADDRESS 0x0400 #define SMBUS_BASE_SIZE 0x10 -/* Temporary addresses used in romstage */ -#define EARLY_GTT_BAR 0xe0000000 -#define EARLY_XHCI_BAR 0xd7000000 -#define EARLY_UART_BAR CONFIG_TTYS0_BASE -#define EARLY_TEMP_MMIO 0xfed08000 - #endif diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h index 232843664a..2773051c03 100644 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ b/src/soc/intel/skylake/include/soc/pei_data.h @@ -38,108 +38,12 @@ typedef void ABI_X86(*tx_byte_func)(unsigned char byte); -enum board_type { - BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */ - BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */ - BOARD_TYPE_USER1, /* SV mobile */ - BOARD_TYPE_USER2, /* SV desktop */ - BOARD_TYPE_USER3, /* SV server */ - BOARD_TYPE_ULT, /* ULT */ - BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */ - BOARD_TYPE_UNKNOWN, -}; - -#define MAX_USB2_PORTS 14 -#define MAX_USB3_PORTS 6 -#define USB_OC_PIN_SKIP 8 - -enum usb2_port_location { - USB_PORT_BACK_PANEL = 0, - USB_PORT_FRONT_PANEL, - USB_PORT_DOCK, - USB_PORT_MINI_PCIE, - USB_PORT_FLEX, - USB_PORT_INTERNAL, - USB_PORT_SKIP, - USB_PORT_NGFF_DEVICE_DOWN, -}; - -struct usb2_port_setting { - /* - * Usb Port Length: - * [16:4] = length in inches in octal format - * [3:0] = decimal point - */ - uint16_t length; - uint8_t enable; - uint8_t oc_pin; - uint8_t location; -} __attribute__((packed)); - -struct usb3_port_setting { - uint8_t enable; - uint8_t oc_pin; - /* - * Set to 0 if trace length is > 5 inches - * Set to 1 if trace length is <= 5 inches - */ - uint8_t fixed_eq; -} __attribute__((packed)); - struct pei_data { uint32_t pei_version; - enum board_type board_type; int boot_mode; int ec_present; - /* Base addresses */ - uint32_t pciexbar; - uint16_t smbusbar; - uint32_t xhcibar; - uint32_t gttbar; - uint32_t pmbase; - uint32_t temp_mmio_base; - uint32_t tseg_size; - - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - int dimm_channel0_disabled; - int dimm_channel1_disabled; - /* Set to 0 for memory down */ - uint8_t spd_addresses[4]; - /* Enable 2x Refresh Mode */ - int ddr_refresh_2x; - /* DQ pins are interleaved on board */ - int dq_pins_interleaved; - /* Limit DDR3 frequency */ - int max_ddr3_freq; - /* Disable self refresh */ - int disable_self_refresh; - /* Disable cmd power/CKEPD */ - int disable_cmd_pwr; - - /* USB port configuration */ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; - - /* - * USB3 board specific PHY tuning - */ - - /* Valid range: 0x69 - 0x80 */ - uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS]; - /* Valid range: 0x80 - 0x9c */ - uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS]; - /* Valid range: 0x39 - 0x80 */ - uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS]; - /* Valid range: 0x3d - 0x4a */ - uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS]; - /* Console output function */ tx_byte_func tx_byte; diff --git a/src/soc/intel/skylake/include/soc/pei_wrapper.h b/src/soc/intel/skylake/include/soc/pei_wrapper.h index 7d37c10e2e..7f4872215d 100644 --- a/src/soc/intel/skylake/include/soc/pei_wrapper.h +++ b/src/soc/intel/skylake/include/soc/pei_wrapper.h @@ -25,25 +25,6 @@ typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); -static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, - uint16_t length, uint8_t enable, - uint8_t oc_pin, uint8_t location) -{ - pei_data->usb2_ports[port].length = length; - pei_data->usb2_ports[port].enable = enable; - pei_data->usb2_ports[port].oc_pin = oc_pin; - pei_data->usb2_ports[port].location = location; -} - -static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, - uint8_t enable, uint8_t oc_pin, - uint8_t fixed_eq) -{ - pei_data->usb3_ports[port].enable = enable; - pei_data->usb3_ports[port].oc_pin = oc_pin; - pei_data->usb3_ports[port].fixed_eq = fixed_eq; -} - void soc_fill_pei_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c index b943224cdc..47198a7b9f 100644 --- a/src/soc/intel/skylake/pei_data.c +++ b/src/soc/intel/skylake/pei_data.c @@ -35,14 +35,5 @@ static void ABI_X86 send_to_console(unsigned char b) void soc_fill_pei_data(struct pei_data *pei_data) { pei_data->pei_version = PEI_VERSION; - pei_data->board_type = BOARD_TYPE_ULT; - pei_data->pciexbar = MCFG_BASE_ADDRESS; - pei_data->smbusbar = SMBUS_BASE_ADDRESS; - pei_data->xhcibar = EARLY_XHCI_BAR; - pei_data->gttbar = EARLY_GTT_BAR; - pei_data->pmbase = ACPI_BASE_ADDRESS; - pei_data->tseg_size = smm_region_size(); - pei_data->temp_mmio_base = EARLY_TEMP_MMIO; pei_data->tx_byte = &send_to_console; - pei_data->ddr_refresh_2x = 1; } -- cgit v1.2.3