From b647e35119c10099b78609f432a7cb9ad3e7e1e2 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 1 Dec 2021 14:33:25 +0530 Subject: soc/intel/alderlake: Add timestamp for cse_fw_sync The patch add timestamp around cse_fw_sync(). TEST=Verified on Brya, cbmem -t: 948:starting CSE firmware sync 1,381,577 (45,227) 949:finished CSE firmware sync 1,459,513 (77,936) Signed-off-by: Sridhar Siricilla Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Maulik V Vaghela --- src/soc/intel/alderlake/romstage/romstage.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index b9d08c8386..ae83d49275 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #define FSP_SMBIOS_MEMORY_INFO_GUID \ @@ -135,8 +136,11 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { + timestamp_add_now(TS_START_CSE_FW_SYNC); cse_fw_sync(); + timestamp_add_now(TS_END_CSE_FW_SYNC); + } /* * Set low maximum temp threshold value used for dynamic thermal sensor -- cgit v1.2.3